43_Conv3d_Max_LogSumExp_ReLU
• fused_gridstride_logsumexp_relu_base
import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
stride: int,
padding: int,
conv_weight: torch.Tensor,
conv_bias: torch.Tensor,
) -> torch.Tensor:
"""
Applies 3D convolution, max pooling, log sum exp, and ReLU activation.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, depth, height, width)
stride (int): Stride of the convolution
padding (int): Padding of the convolution
conv_weight (torch.Tensor): Convolution weight tensor
conv_bias (torch.Tensor): Convolution bias tensor
Returns:
torch.Tensor: Output tensor after applying convolution, max pooling, logsumexp and ReLU
"""
x = F.conv3d(x, conv_weight, bias=conv_bias, stride=stride, padding=padding)
x = F.max_pool3d(x, kernel_size=2, stride=2)
x = torch.logsumexp(x, dim=1, keepdim=True)
x = F.relu(x)
return x
class Model(nn.Module):
"""
Model that performs a 3D convolution, max pooling, log sum exp, and ReLU activation.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride, padding):
super(Model, self).__init__()
conv = nn.Conv3d(
in_channels, out_channels, kernel_size, stride=stride, padding=padding
)
self.conv_weight = nn.Parameter(conv.weight)
self.conv_bias = nn.Parameter(
conv.bias
+ torch.randn(
conv.bias.shape, device=conv.bias.device, dtype=conv.bias.dtype
)
* 0.02
)
def forward(self, x, stride, padding, fn=module_fn):
return fn(x, stride, padding, self.conv_weight, self.conv_bias)
batch_size = 128
in_channels = 3
out_channels = 16
depth, height, width = 16, 32, 32
kernel_size = 3
stride = 1
padding = 1
def get_inputs():
return [torch.randn(batch_size, in_channels, depth, height, width), stride, padding]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Model that performs a 3D convolution, max pooling, log sum exp, and ReLU activation.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride, padding):
super(Model, self).__init__()
self.conv = nn.Conv3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)
self.conv.bias = nn.Parameter(self.conv.bias + torch.randn(self.conv.bias.shape, device=self.conv.bias.device, dtype=self.conv.bias.dtype) * 0.02)
self.max_pool = nn.MaxPool3d(kernel_size=2, stride=2)
def forward(self, x):
"""
Args:
x: Input tensor of shape (batch_size, in_channels, depth, height, width)
Returns:
Output tensor of shape (batch_size, out_channels, depth', height', width')
"""
x = self.conv(x)
x = self.max_pool(x)
x = torch.logsumexp(x, dim=1, keepdim=True)
x = torch.relu(x)
return x
batch_size = 128
in_channels = 3
out_channels = 16
depth, height, width = 16, 32, 32
kernel_size = 3
stride = 1
padding = 1
def get_inputs():
return [torch.randn(batch_size, in_channels, depth, height, width)]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding]
/*
This kernel fuses the logsumexp reduction over the channel dimension with ReLU activation.
It uses a grid-stride loop to handle all output elements, and applies loop unrolling
for the inner channel loop to improve instruction-level parallelism and reduce loop overhead.
*/
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
#include <cfloat>
#include <cmath>
// Kernel definition
__global__ void fused_gridstride_logsumexp_relu_kernel(const float* __restrict__ input,
float* __restrict__ output,
const int N, const int C,
const int D, const int H, const int W) {
// Total number of output elements (each corresponds to a reduction over channels)
const int total = N * D * H * W;
// spatial_stride is the stride between different channels for a fixed (n,d,h,w)
const int spatial_stride = D * H * W;
// Compute global thread id and total number of threads
int tid = blockIdx.x * blockDim.x + threadIdx.x;
int num_threads = blockDim.x * gridDim.x;
// Grid-stride loop: each thread processes multiple (n, d, h, w) positions
for (int idx = tid; idx < total; idx += num_threads) {
// Decode the linear index into (n, d, h, w): note that the tensor layout is [N, C, D, H, W]
int tmp = idx;
int w = tmp % W;
tmp /= W;
int h = tmp % H;
tmp /= H;
int d = tmp % D;
int n = tmp / D;
// Compute the base index for the reduction over channels
int base = n * (C * spatial_stride) + d * (H * W) + h * W + w;
// First pass: compute the maximum over channels for numerical stability
float local_max = -FLT_MAX;
#pragma unroll
for (int c = 0; c < C; ++c) {
float val = input[base + c * spatial_stride];
local_max = fmaxf(local_max, val);
}
// Second pass: accumulate the sum of exponentials
float sum_exp = 0.0f;
#pragma unroll
for (int c = 0; c < C; ++c) {
float val = input[base + c * spatial_stride];
sum_exp += expf(val - local_max);
}
// Compute the logsumexp result and apply ReLU
float result = local_max + logf(sum_exp);
result = fmaxf(0.0f, result);
// Store the result into the output tensor
output[idx] = result;
}
}
// Host function: performs conv3d and max_pool3d using PyTorch, then fuses logsumexp and ReLU using the custom kernel
torch::Tensor forward(
torch::Tensor x,
int64_t stride,
int64_t padding,
torch::Tensor conv_weight,
torch::Tensor conv_bias) {
// Ensure the tensors are contiguous
x = x.contiguous();
conv_weight = conv_weight.contiguous();
conv_bias = conv_bias.contiguous();
// Execute 3D convolution using PyTorch
auto conv_result = torch::conv3d(x, conv_weight, conv_bias, {stride, stride, stride}, {padding, padding, padding});
// Execute 3D max pooling using PyTorch with kernel size 2 and stride 2
auto pool_result = torch::max_pool3d(conv_result, {2, 2, 2}, {2, 2, 2});
// Dimensions of the pooled tensor are [N, C, D, H, W]
int N = pool_result.size(0);
int C = pool_result.size(1);
int D = pool_result.size(2);
int H = pool_result.size(3);
int W = pool_result.size(4);
// Create output tensor with shape [N, 1, D, H, W]
auto output = torch::empty({N, 1, D, H, W}, pool_result.options());
// Total number of output elements
int total = N * D * H * W;
const int block_size = 256;
int num_blocks = (total + block_size - 1) / block_size;
// Launch the fused kernel with grid-stride loop and unrolling for improved efficiency
fused_gridstride_logsumexp_relu_kernel<<<num_blocks, block_size>>>(
pool_result.data_ptr<float>(),
output.data_ptr<float>(),
N, C, D, H, W
);
cudaDeviceSynchronize();
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &forward, "Fused grid-stride kernel for logsumexp and ReLU activation");
}
Metric | Value | Unit | Variance | Samples |
---|---|---|---|---|
Executed Ipc Active | 1.646 | inst/cycle | 0.000 | 5 |
Executed Ipc Elapsed | 1.204 | inst/cycle | 0.001 | 5 |
Issue Slots Busy | 41.936 | % | 0.166 | 5 |
Issued Ipc Active | 1.678 | inst/cycle | 0.000 | 5 |
SM Busy | 41.936 | % | 0.166 | 5 |
Memory Throughput | 1589080817856.674 | byte/second | 856259616801435942912.000 | 5 |
Mem Busy | 30.244 | % | 0.290 | 5 |
Max Bandwidth | 47.604 | % | 0.766 | 5 |
L1/TEX Hit Rate | 42.160 | % | 0.001 | 5 |
L2 Hit Rate | 21.860 | % | 0.017 | 5 |
Mem Pipes Busy | 12.728 | % | 0.060 | 5 |
Warp Cycles Per Issued Instruction | 31.352 | cycle | 0.002 | 5 |
Warp Cycles Per Executed Instruction | 31.978 | cycle | 0.002 | 5 |
Avg. Active Threads Per Warp | 32.000 | 0.000 | 5 | |
Avg. Not Predicated Off Threads Per Warp | 29.960 | 0.000 | 5 | |
Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
Max Cluster Size | 8.000 | block | 0.000 | 5 |
Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
Cluster Occupancy | 0.000 | % | 0.000 | 5 |
Block Limit SM | 32.000 | block | 0.000 | 5 |
Block Limit Registers | 8.000 | block | 0.000 | 5 |
Block Limit Shared Mem | 32.000 | block | 0.000 | 5 |
Block Limit Warps | 8.000 | block | 0.000 | 5 |
Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
Achieved Occupancy | 82.656 | % | 0.024 | 5 |
Achieved Active Warps Per SM | 52.900 | warp | 0.010 | 5 |
Rule | Description |
---|---|
INF HighPipeUtilization | ALU is the highest-utilized pipeline (25.3%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck. |
INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (82.5%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
Operation / Metric | Value | Unit |
---|---|---|
aten::to | ||
CPU Time | 291159.89 | μs |
Device Time | 2589.17 | μs |
Self CPU Time | 62.54 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::conv3d | ||
CPU Time | 412798.68 | μs |
Device Time | 4865538.45 | μs |
Self CPU Time | 13869.91 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::convolution | ||
CPU Time | 398928.77 | μs |
Device Time | 4865538.45 | μs |
Self CPU Time | 18766.90 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::_convolution | ||
CPU Time | 380161.87 | μs |
Device Time | 4865538.45 | μs |
Self CPU Time | 35239.75 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::cudnn_convolution | ||
CPU Time | 261834.87 | μs |
Device Time | 3953898.06 | μs |
Self CPU Time | 178590.11 | μs |
Self Device Time | 3953898.06 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
sm80_xmma_fprop_implicit_gemm_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize128x32x8_stage3_warpsize2x2x1_g1_ffma_aligna4_alignc4_execute_kernel__5x_cudnn | ||
CPU Time | 0.00 | μs |
Device Time | 3953895.18 | μs |
Self CPU Time | 0.00 | μs |
Self Device Time | 3953895.18 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
cudaDeviceSynchronize | ||
CPU Time | 6142777.98 | μs |
Device Time | 86142.39 | μs |
Self CPU Time | 6142777.98 | μs |
Self Device Time | 86142.39 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
45286 warnings generated when compiling for host. Suppressed 45325 warnings (45278 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.