6_Conv3d_Softmax_MaxPool_MaxPool
• fused_double_maxpool_base
import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
conv_weight: torch.Tensor,
conv_bias: torch.Tensor,
) -> torch.Tensor:
"""Applies 3D convolution, softmax activation, and two max pooling operations.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, depth, height, width)
conv_weight (torch.Tensor): Convolution weight tensor of shape
(out_channels, in_channels, kernel_size, kernel_size, kernel_size)
conv_bias (torch.Tensor): Bias tensor for convolution of shape (out_channels)
Returns:
torch.Tensor: Output tensor after applying convolution, softmax and max pooling,
with shape (batch_size, out_channels, depth', height', width') where:
depth' = ((depth - kernel_size + 1) // 4)
height' = ((height - kernel_size + 1) // 4)
width' = ((width - kernel_size + 1) // 4)
The //4 comes from two max pooling operations with kernel_size=2
"""
x = F.conv3d(x, conv_weight, conv_bias, stride=1, padding=0)
x = F.softmax(x, dim=1)
x = F.max_pool3d(x, kernel_size=2)
x = F.max_pool3d(x, kernel_size=2)
return x
class Model(nn.Module):
"""
Model that performs a 3D convolution, applies Softmax, and performs two max pooling operations.
"""
def __init__(self, in_channels, out_channels, kernel_size, pool_kernel_size):
super(Model, self).__init__()
conv = nn.Conv3d(in_channels, out_channels, kernel_size, padding=1)
self.conv_weight = nn.Parameter(conv.weight)
self.conv_bias = nn.Parameter(conv.bias)
def forward(self, x, fn=module_fn):
return fn(x, self.conv_weight, self.conv_bias)
batch_size = 128
in_channels = 3
out_channels = 16
depth, height, width = 16, 32, 32
kernel_size = 3
pool_kernel_size = 2
def get_inputs():
return [torch.randn(batch_size, in_channels, depth, height, width)]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, pool_kernel_size]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Model that performs a 3D convolution, applies Softmax, and performs two max pooling operations.
"""
def __init__(self, in_channels, out_channels, kernel_size, pool_kernel_size):
super(Model, self).__init__()
self.conv = nn.Conv3d(in_channels, out_channels, kernel_size)
self.pool1 = nn.MaxPool3d(pool_kernel_size)
self.pool2 = nn.MaxPool3d(pool_kernel_size)
def forward(self, x):
"""
Args:
x: Input tensor of shape (batch_size, in_channels, depth, height, width)
Returns:
Output tensor of shape (batch_size, out_channels, depth', height', width') where depth', height', width' are the dimensions after pooling.
"""
x = self.conv(x)
x = torch.softmax(x, dim=1)
x = self.pool1(x)
x = self.pool2(x)
return x
batch_size = 128
in_channels = 3
out_channels = 16
depth, height, width = 16, 32, 32
kernel_size = 3
pool_kernel_size = 2
def get_inputs():
return [torch.randn(batch_size, in_channels, depth, height, width)]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, pool_kernel_size]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <cfloat>
// Fused kernel to perform two sequential max pooling operations as one 4x4x4 pooling
// It fuses the two max pooling steps (each with kernel size 2 and stride 2) into one kernel
// that performs a 4x4x4 reduction using shared memory and warp-level primitives.
__global__ void fused_maxpool_kernel(
const float* __restrict__ input,
float* __restrict__ output,
int N, int C, int D, int H, int W,
int outD, int outH, int outW
) {
// Grid mapping:
// blockIdx.x -> output width index (outW)
// blockIdx.y -> output height index (outH)
// blockIdx.z -> combined index for (N, C, outD): index = n * (C*outD) + c * outD + d_out
int out_w = blockIdx.x;
int out_h = blockIdx.y;
int index = blockIdx.z;
int n = index / (C * outD);
int rem = index % (C * outD);
int c = rem / outD;
int out_d = rem % outD;
// Compute starting indices in the input tensor for a 4x4x4 pooling window
int d_start = out_d * 4;
int h_start = out_h * 4;
int w_start = out_w * 4;
// Each block uses 64 threads to reduce a 4x4x4 window (64 elements)
int tid = threadIdx.x;
// Map thread id [0,63] to 3D coordinates in 4x4x4 window
int local_d = tid / 16; // [0, 3]
int local_h = (tid % 16) / 4; // [0, 3]
int local_w = tid % 4; // [0, 3]
int d = d_start + local_d;
int h = h_start + local_h;
int w = w_start + local_w;
float val = -FLT_MAX;
if (d < D && h < H && w < W) {
int input_idx = n * (C * D * H * W) + c * (D * H * W) + d * (H * W) + h * W + w;
val = input[input_idx];
}
// Perform warp-level reduction using __shfl_down_sync
unsigned int mask = 0xffffffff;
#pragma unroll
for (int offset = 16; offset > 0; offset /= 2) {
float other = __shfl_down_sync(mask, val, offset);
val = fmaxf(val, other);
}
// Each warp's leader writes its result to shared memory
__shared__ float shared[2];
int warp_id = tid / 32; // two warps per block
if ((tid & 31) == 0) {
shared[warp_id] = val;
}
__syncthreads();
// Final reduction across warps in the first warp
if (tid < 32) {
if (tid < 2) {
float v = shared[tid];
#pragma unroll
for (int offset = 1; offset < 2; offset *= 2) {
float other = __shfl_down_sync(mask, v, offset);
v = fmaxf(v, other);
}
if (tid == 0) {
int out_idx = n * (C * outD * outH * outW) + c * (outD * outH * outW) + out_d * (outH * outW) + out_h * outW + out_w;
output[out_idx] = v;
}
}
}
}
// Forward function implementing 6_Conv3d_Softmax_MaxPool_MaxPool with fused double max pooling
// This function applies 3D convolution, softmax activation over channels, and then fuses two
// consecutive max pooling operations into one optimized CUDA kernel.
torch::Tensor forward(
torch::Tensor x,
torch::Tensor conv_weight,
torch::Tensor conv_bias
) {
// Ensure tensors are contiguous
x = x.contiguous();
conv_weight = conv_weight.contiguous();
conv_bias = conv_bias.contiguous();
// Apply 3D convolution
auto conv_output = at::conv3d(x, conv_weight, conv_bias, {1, 1, 1}, {0, 0, 0});
// Apply softmax over the channel dimension
auto softmax_output = at::softmax(conv_output, /*dim=*/1);
// Get dimensions (assuming softmax_output is [N, C, D, H, W])
int N = softmax_output.size(0);
int C = softmax_output.size(1);
int D = softmax_output.size(2);
int H = softmax_output.size(3);
int W = softmax_output.size(4);
// Compute output dimensions after two pooling operations fused as a 4x4x4 pooling
int outD = D / 4;
int outH = H / 4;
int outW = W / 4;
auto options = softmax_output.options();
auto output = torch::empty({N, C, outD, outH, outW}, options);
// Launch the fused max pooling kernel
// Grid: (outW, outH, N * C * outD) so that each block computes one output element
dim3 grid(outW, outH, N * C * outD);
int threads = 64; // one thread per element in the 4x4x4 window
fused_maxpool_kernel<<<grid, threads>>>(
softmax_output.data_ptr<float>(),
output.data_ptr<float>(),
N, C, D, H, W,
outD, outH, outW
);
cudaDeviceSynchronize();
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &forward, "Optimized CUDA forward function with fused double max pooling");
}
Metric | Value | Unit | Variance | Samples |
---|---|---|---|---|
Executed Ipc Active | 1.910 | inst/cycle | 0.000 | 5 |
Executed Ipc Elapsed | 1.870 | inst/cycle | 0.000 | 5 |
Issue Slots Busy | 47.698 | % | 0.001 | 5 |
Issued Ipc Active | 1.910 | inst/cycle | 0.000 | 5 |
SM Busy | 47.698 | % | 0.001 | 5 |
Memory Throughput | 474006970323.882 | byte/second | 37735794039516824.000 | 5 |
Mem Busy | 25.490 | % | 0.000 | 5 |
Max Bandwidth | 19.950 | % | 0.000 | 5 |
L1/TEX Hit Rate | 0.344 | % | 0.000 | 5 |
L2 Hit Rate | 65.094 | % | 0.022 | 5 |
Mem Pipes Busy | 32.772 | % | 0.000 | 5 |
Warp Cycles Per Issued Instruction | 11.718 | cycle | 0.000 | 5 |
Warp Cycles Per Executed Instruction | 11.718 | cycle | 0.000 | 5 |
Avg. Active Threads Per Warp | 29.710 | 0.000 | 5 | |
Avg. Not Predicated Off Threads Per Warp | 25.400 | 0.000 | 5 | |
Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
Max Cluster Size | 8.000 | block | 0.000 | 5 |
Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
Cluster Occupancy | 0.000 | % | 0.000 | 5 |
Block Limit SM | 32.000 | block | 0.000 | 5 |
Block Limit Registers | 42.000 | block | 0.000 | 5 |
Block Limit Shared Mem | 56.000 | block | 0.000 | 5 |
Block Limit Warps | 32.000 | block | 0.000 | 5 |
Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
Achieved Occupancy | 35.786 | % | 0.001 | 5 |
Achieved Active Warps Per SM | 22.902 | warp | 0.000 | 5 |
Rule | Description |
---|---|
INF HighPipeUtilization | ALU is the highest-utilized pipeline (37.8%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck. |
INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (35.8%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
Operation / Metric | Value | Unit |
---|---|---|
aten::conv3d | ||
CPU Time | 371563.81 | μs |
Device Time | 4435435.84 | μs |
Self CPU Time | 12168.90 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::convolution | ||
CPU Time | 359394.90 | μs |
Device Time | 4435435.84 | μs |
Self CPU Time | 18764.82 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::_convolution | ||
CPU Time | 340630.08 | μs |
Device Time | 4435435.84 | μs |
Self CPU Time | 31865.72 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::cudnn_convolution | ||
CPU Time | 234391.76 | μs |
Device Time | 3845198.38 | μs |
Self CPU Time | 168802.25 | μs |
Self Device Time | 3845198.38 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
sm80_xmma_fprop_implicit_gemm_indexed_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize32x32x8_stage3_warpsize1x2x1_g1_ffma_aligna4_alignc4_execute_kernel__5x_cudnn | ||
CPU Time | 0.00 | μs |
Device Time | 3845195.85 | μs |
Self CPU Time | 0.00 | μs |
Self Device Time | 3845195.85 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
cudaDeviceSynchronize | ||
CPU Time | 6683057.73 | μs |
Device Time | 261613.75 | μs |
Self CPU Time | 6683057.73 | μs |
Self Device Time | 261613.75 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
45287 warnings generated when compiling for host. Suppressed 45323 warnings (45276 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.