79_conv_transposed_1D_asymmetric_input_square_kernel___padded____strided____dilated__ • conv_transpose1d_shared_tile_sync_baseimport torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
weight: torch.Tensor,
bias: torch.Tensor,
stride: int,
padding: int,
dilation: int,
) -> torch.Tensor:
"""
Performs a transposed 1D convolution operation with asymmetric input and square kernel. Supports padding, striding, and dilation.
Args:
x (torch.Tensor): Input tensor
weight (torch.Tensor): Convolution weights
bias (torch.Tensor): Bias tensor (optional)
stride (int): Stride of the convolution
padding (int): Padding applied to the input
dilation (int): Spacing between kernel elements
Returns:
torch.Tensor: Output tensor
"""
return F.conv_transpose1d(
x, weight, bias=bias, stride=stride, padding=padding, dilation=dilation
)
class Model(nn.Module):
"""
Performs a transposed 1D convolution operation with asymmetric input and square kernel.
Supports padding, striding, and dilation.
Args:
in_channels (int): Number of channels in the input tensor.
out_channels (int): Number of channels produced by the convolution.
kernel_size (int): Size of the square convolution kernel.
stride (int): Stride of the convolution.
padding (int): Padding applied to the input.
dilation (int): Spacing between kernel elements.
bias (bool): If `True`, adds a learnable bias to the output.
"""
def __init__(
self,
in_channels: int,
out_channels: int,
kernel_size: int,
stride: int,
padding: int,
dilation: int,
bias: bool,
):
super(Model, self).__init__()
self.conv_transpose1d = nn.ConvTranspose1d(
in_channels,
out_channels,
kernel_size,
stride=stride,
padding=padding,
dilation=dilation,
bias=bias,
)
# Copy the initialized parameters
self.weight = nn.Parameter(self.conv_transpose1d.weight.clone())
self.bias = nn.Parameter(self.conv_transpose1d.bias.clone()) if bias else None
self.stride = stride
self.padding = padding
self.dilation = dilation
def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
return fn(
x,
self.weight,
self.bias,
self.stride,
self.padding,
self.dilation,
)
# Constants
batch_size = 16
in_channels = 32
out_channels = 64
kernel_size = 3
length = 128
stride = 2
padding = 1
dilation = 2
bias = False
def get_inputs():
x = torch.randn(batch_size, in_channels, length)
return [x]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding, dilation, bias]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Performs a transposed 1D convolution operation with asymmetric input and square kernel.
Supports padding, striding, and dilation.
Args:
in_channels (int): Number of channels in the input tensor.
out_channels (int): Number of channels produced by the convolution.
kernel_size (int): Size of the square convolution kernel.
stride (int, optional): Stride of the convolution. Defaults to 1.
padding (int, optional): Padding applied to the input. Defaults to 0.
dilation (int, optional): Spacing between kernel elements. Defaults to 1.
bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.
"""
def __init__(
self,
in_channels: int,
out_channels: int,
kernel_size: int,
stride: int = 1,
padding: int = 0,
dilation: int = 1,
bias: bool = False,
):
super(Model, self).__init__()
self.conv1d_transpose = nn.ConvTranspose1d(
in_channels,
out_channels,
kernel_size,
stride=stride,
padding=padding,
dilation=dilation,
bias=bias,
)
def forward(self, x: torch.Tensor) -> torch.Tensor:
"""
Performs the transposed 1D convolution.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, length).
Returns:
torch.Tensor: Output tensor of shape (batch_size, out_channels, length_out).
"""
return self.conv1d_transpose(x)
# Constants
batch_size = 16
in_channels = 32
out_channels = 64
kernel_size = 3
length = 128
stride = 2
padding = 1
dilation = 2
bias = False
def get_inputs():
x = torch.randn(batch_size, in_channels, length)
return [x]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding, dilation, bias]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
// Helper function to compute the output length
inline int compute_output_length(int input_length, int stride, int padding, int dilation, int kernel_size) {
return (input_length - 1) * stride - 2 * padding + dilation * (kernel_size - 1) + 1;
}
// Kernel that uses shared memory to load the weight tile for a fixed output channel
// Each block is mapped to a unique (batch, out_channel) pair. Threads in the block then compute
// the output values along the output length dimension.
// __syncthreads() is used only once after loading the shared memory tile to ensure consistency.
__global__ void conv_transpose1d_shared_kernel(
const float* __restrict__ x_ptr,
const float* __restrict__ weight_ptr,
const float* __restrict__ bias_ptr,
float* __restrict__ output_ptr,
int in_channels,
int input_length,
int output_length,
int kernel_size,
int stride,
int padding,
int dilation
) {
// Map each block to a unique (batch, output channel) pair
int b = blockIdx.x; // batch index
int oc = blockIdx.y; // output channel index
// Allocate shared memory for the weight tile: [in_channels x kernel_size]
extern __shared__ float s_weight[];
int tile_size = in_channels * kernel_size;
// Each thread loads part of the weight tile from global memory into shared memory
// Global weight shape: [in_channels, out_channels, kernel_size]
// For the given oc, the element weight[ic, oc, k] is at index: ic * (out_channels * kernel_size) + oc * kernel_size + k
for (int idx = threadIdx.x; idx < tile_size; idx += blockDim.x) {
int ic = idx / kernel_size;
int k = idx % kernel_size;
int weight_idx = ic * (gridDim.y * kernel_size) + oc * kernel_size + k;
s_weight[idx] = weight_ptr[weight_idx];
}
__syncthreads(); // Ensure the shared weight tile is fully loaded before use
// Each thread processes output elements along the output_length dimension
for (int o = threadIdx.x; o < output_length; o += blockDim.x) {
float sum = 0.0f;
// Loop over kernel positions
for (int k = 0; k < kernel_size; ++k) {
int i_pos = o + padding - k * dilation;
if (i_pos % stride != 0) continue;
int i = i_pos / stride;
if (i < 0 || i >= input_length) continue;
// Accumulate over input channels
for (int ic = 0; ic < in_channels; ++ic) {
int x_idx = b * (in_channels * input_length) + ic * input_length + i;
sum += x_ptr[x_idx] * s_weight[ic * kernel_size + k];
}
}
if (bias_ptr) {
sum += bias_ptr[oc];
}
int out_idx = b * (gridDim.y * output_length) + oc * output_length + o;
output_ptr[out_idx] = sum;
}
}
// Forward function for the CUDA kernel
torch::Tensor forward_cuda(
torch::Tensor x,
torch::Tensor weight,
torch::optional<torch::Tensor> bias,
int stride,
int padding,
int dilation
) {
TORCH_CHECK(x.device().is_cuda(), "x must be a CUDA tensor");
TORCH_CHECK(weight.device().is_cuda(), "weight must be a CUDA tensor");
TORCH_CHECK(x.dim() == 3, "x must be 3D (batch, in_channels, input_length)");
TORCH_CHECK(weight.dim() == 3, "weight must be 3D (in_channels, out_channels, kernel_size)");
x = x.contiguous();
weight = weight.contiguous();
torch::Tensor bias_contig;
const float* bias_ptr = nullptr;
if (bias.has_value()) {
bias_contig = bias->contiguous();
TORCH_CHECK(bias_contig.device().is_cuda(), "bias must be a CUDA tensor");
TORCH_CHECK(bias_contig.dim() == 1, "bias must be 1D");
bias_ptr = bias_contig.data_ptr<float>();
}
int batch_size = x.size(0);
int in_channels = x.size(1);
int input_length = x.size(2);
int out_channels = weight.size(1);
int kernel_size = weight.size(2);
TORCH_CHECK(weight.size(0) == in_channels, "weight's in_channels must match x's in_channels");
if (bias.has_value()) {
TORCH_CHECK(bias_contig.size(0) == out_channels, "bias size must match out_channels");
}
int output_length = compute_output_length(input_length, stride, padding, dilation, kernel_size);
auto output = torch::zeros({batch_size, out_channels, output_length}, x.options());
// Configure grid: each block computes one (batch, out_channel) pair
dim3 grid(batch_size, out_channels);
int threads_per_block = 256;
// Shared memory size needed per block: in_channels * kernel_size * sizeof(float)
size_t shared_mem_size = in_channels * kernel_size * sizeof(float);
conv_transpose1d_shared_kernel<<<grid, threads_per_block, shared_mem_size>>>(
x.data_ptr<float>(),
weight.data_ptr<float>(),
bias_ptr,
output.data_ptr<float>(),
in_channels,
input_length,
output_length,
kernel_size,
stride,
padding,
dilation
);
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &forward_cuda, "ConvTranspose1D forward (CUDA) with shared memory optimization",
py::arg("x"), py::arg("weight"), py::arg("bias") = py::none(),
py::arg("stride"), py::arg("padding"), py::arg("dilation"));
}
| Metric | Value | Unit | Variance | Samples |
|---|---|---|---|---|
| Executed Ipc Active | 2.442 | inst/cycle | 0.000 | 5 |
| Executed Ipc Elapsed | 2.016 | inst/cycle | 0.000 | 5 |
| Issue Slots Busy | 61.466 | % | 0.076 | 5 |
| Issued Ipc Active | 2.460 | inst/cycle | 0.000 | 5 |
| SM Busy | 61.466 | % | 0.076 | 5 |
| Memory Throughput | 17271809692.770 | byte/second | 6842965512488033.000 | 5 |
| Mem Busy | 47.260 | % | 0.067 | 5 |
| Max Bandwidth | 45.926 | % | 0.054 | 5 |
| L1/TEX Hit Rate | 84.304 | % | 0.000 | 5 |
| L2 Hit Rate | 103.436 | % | 0.570 | 5 |
| Mem Pipes Busy | 45.916 | % | 0.060 | 5 |
| Warp Cycles Per Issued Instruction | 18.384 | cycle | 0.009 | 5 |
| Warp Cycles Per Executed Instruction | 18.492 | cycle | 0.010 | 5 |
| Avg. Active Threads Per Warp | 18.830 | 0.000 | 5 | |
| Avg. Not Predicated Off Threads Per Warp | 18.030 | 0.000 | 5 | |
| Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
| Max Cluster Size | 8.000 | block | 0.000 | 5 |
| Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
| Cluster Occupancy | 0.000 | % | 0.000 | 5 |
| Block Limit SM | 32.000 | block | 0.000 | 5 |
| Block Limit Registers | 8.000 | block | 0.000 | 5 |
| Block Limit Shared Mem | 23.000 | block | 0.000 | 5 |
| Block Limit Warps | 8.000 | block | 0.000 | 5 |
| Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
| Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
| Achieved Occupancy | 70.592 | % | 0.060 | 5 |
| Achieved Active Warps Per SM | 45.180 | warp | 0.024 | 5 |
| Rule | Description |
|---|---|
| INF HighPipeUtilization | FMA is the highest-utilized pipeline (33.8%) based on active cycles, taking into account the rates of its different instructions. It executes 32-bit floating point (FADD, FMUL, FMAD, ...) and integer (IMUL, IMAD) operations. It is well-utilized, but should not be a bottleneck. |
| WRN ThreadDivergence | Instructions are executed in warps, which are groups of 32 threads. Optimal instruction throughput is achieved if all 32 threads of a warp execute the same instruction. The chosen launch configuration, early thread completion, and divergent flow control can significantly lower the number of active threads in a warp per cycle. This kernel achieves an average of 18.8 threads being active per cycle. This is further reduced to 18.0 threads per warp due to predication. The compiler may use predication to avoid an actual branch. Instead, all instructions are scheduled, but a per-thread condition code or predicate controls which threads execute the instructions. Try to avoid different execution paths within a warp when possible. In addition, ensure your kernel makes use of Independent Thread Scheduling, which allows a warp to reconverge after a data-dependent conditional block by explicitly calling __syncwarp(). |
| WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (70.5%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
| Operation / Metric | Value | Unit |
|---|---|---|
| aten::to | ||
| CPU Time | 460615.65 | μs |
| Device Time | 16.71 | μs |
| Self CPU Time | 56.66 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zeros | ||
| CPU Time | 6283855.88 | μs |
| Device Time | 181115.58 | μs |
| Self CPU Time | 138784.85 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zero_ | ||
| CPU Time | 6708203.96 | μs |
| Device Time | 7221173.65 | μs |
| Self CPU Time | 318552.40 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::fill_ | ||
| CPU Time | 6389652.91 | μs |
| Device Time | 7221173.65 | μs |
| Self CPU Time | 391240.98 | μs |
| Self Device Time | 7221173.65 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaLaunchKernel | ||
| CPU Time | 6328785.64 | μs |
| Device Time | 2762.76 | μs |
| Self CPU Time | 6328785.64 | μs |
| Self Device Time | 2762.76 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| conv_transpose1d_shared_kernel(float const*, float const*, float const*, float*, int, int, int, int, int, int, int) | ||
| CPU Time | 0.00 | μs |
| Device Time | 1265220.95 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 1265220.95 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaEventRecord | ||
| CPU Time | 197095.08 | μs |
| Device Time | 1167425.26 | μs |
| Self CPU Time | 197095.08 | μs |
| Self Device Time | 1167425.26 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>) | ||
| CPU Time | 0.00 | μs |
| Device Time | 7040058.07 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 7040058.07 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
45295 warnings generated when compiling for host. Suppressed 45326 warnings (45279 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.