← Back to Leaderboard

The AI CUDA Engineer 👷

94_MSELoss • mse_min_sync_edit_1

Level 1 • Task 94
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(predictions: torch.Tensor, targets: torch.Tensor) -> torch.Tensor:
    """
    Computes the Mean Squared Error loss for regression tasks.

    Args:
        predictions (torch.Tensor): Predicted values.
        targets (torch.Tensor): Target values.

    Returns:
        torch.Tensor: Mean Squared Error loss.
    """
    return F.mse_loss(predictions, targets, reduction="mean")


class Model(nn.Module):
    """
    A model that computes the Mean Squared Error loss for regression tasks.

    Parameters:
        None
    """

    def __init__(self):
        super(Model, self).__init__()

    def forward(self, predictions, targets, fn=module_fn):
        return fn(predictions, targets)


batch_size = 128
input_shape = (4096,)
dim = 1


def get_inputs():
    return [
        torch.randn(batch_size, *input_shape),
        torch.randn(batch_size, *input_shape),
    ]


def get_init_inputs():
    return []

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    A model that computes the Mean Squared Error loss for regression tasks.

    Parameters:
        None
    """
    def __init__(self):
        super(Model, self).__init__()

    def forward(self, predictions, targets):
        return torch.mean((predictions - targets) ** 2)

batch_size = 128
input_shape = (4096, )
dim = 1

def get_inputs():
    return [torch.randn(batch_size, *input_shape), torch.randn(batch_size, *input_shape)]

def get_init_inputs():
    return []
Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name 94_MSELoss
Level ID 1
Task ID 94
Kernel Name mse_min_sync_edit_1
CUDA Speedup (Native) 1.034x
CUDA Speedup (Compile) 2.036x
CUDA Runtime 0.016 ms
PyTorch Runtime (Native) 0.017 ms
PyTorch Runtime (Compile) 0.033 ms
Correct True
Max Diff (vs. Reference) 0.000000
Model bedrock/anthropic.claude-3-5-sonnet-20241022-v2:0
Temperature 0.00
View Experiment Progress Details

Related Kernels (Level 1, Task 94 • 94_MSELoss)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 optimized_thread_indexing_base 0.02 1.03 2.04
🥇 coalesced_shfl_mse_base 0.02 1.03 2.04
🥇 efficient_mse_base 0.02 1.03 2.04
🥇 mse_unrolled_optimized_base 0.02 1.03 2.04
🥇 mse_min_sync_edit_1 0.02 1.03 2.04
🥇 vectorized_ldg_mse_base 0.02 1.03 2.04
🥇 optimized_grid_stride_warp_reduce_base 0.02 1.03 2.04
🥇 mse_1d_optimized_indexing_base 0.02 1.03 2.04
🥇 mse_unrolled_optimized_edit_1 0.02 1.03 2.04
🥇 mse_warp_reduction_base 0.02 1.03 2.04
🥇 mse_unroll_pragma_base_base 0.02 1.03 2.04
🥇 mse_blocksize_experiment_base 0.02 1.03 2.04
🥇 mse_ldg_vectorized_edit_edit_1 0.02 1.03 2.04
🥇 mse_ldg_vectorized_edit_base 0.02 1.03 2.04
15 optimized_block_size_mse_base 0.02 0.97 1.92
15 stride_mse_loss_base 0.02 0.97 1.92
15 warp_uniform_mse_base 0.02 0.97 1.92
15 block_size_experimentation_base_base 0.02 0.97 1.92
15 optimized_mse_forward_base 0.02 0.97 1.92
15 warp_aligned_mse_base_base 0.02 0.97 1.92 
#include <pybind11/pybind11.h>
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>

static const int BLOCK_SIZE = 256;

template <typename scalar_t>
__global__ void mse_forward_kernel_min_sync(
    const scalar_t* __restrict__ preds,
    const scalar_t* __restrict__ tgts,
    double* __restrict__ sum_out,
    const int64_t num_elements
) {
    // Each thread maintains its own accumulator
    double thread_sum = 0.0;
    
    // Use vector loads for better memory throughput when possible
    if constexpr (sizeof(scalar_t) == sizeof(float)) {
        const float2* preds2 = reinterpret_cast<const float2*>(preds);
        const float2* tgts2 = reinterpret_cast<const float2*>(tgts);
        
        // Process two elements at a time
        for (int idx = blockIdx.x * blockDim.x + threadIdx.x; 
             idx < num_elements/2; 
             idx += blockDim.x * gridDim.x) {
            float2 pred_vec = __ldcg(&preds2[idx]); // Cache hint for global loads
            float2 tgt_vec = __ldcg(&tgts2[idx]);
            
            double diff1 = static_cast<double>(pred_vec.x) - static_cast<double>(tgt_vec.x);
            double diff2 = static_cast<double>(pred_vec.y) - static_cast<double>(tgt_vec.y);
            thread_sum += diff1 * diff1 + diff2 * diff2;
        }
        
        // Handle remaining odd element if necessary
        if (blockIdx.x * blockDim.x + threadIdx.x == 0 && (num_elements & 1)) {
            int last_idx = num_elements - 1;
            double diff = static_cast<double>(preds[last_idx]) - static_cast<double>(tgts[last_idx]);
            thread_sum += diff * diff;
        }
    } else {
        // Regular processing for non-float types
        for (int idx = blockIdx.x * blockDim.x + threadIdx.x; 
             idx < num_elements; 
             idx += blockDim.x * gridDim.x) {
            double diff = static_cast<double>(preds[idx]) - static_cast<double>(tgts[idx]);
            thread_sum += diff * diff;
        }
    }

    // Warp-level reduction first (no sync needed within a warp)
    const unsigned int FULL_WARP_MASK = 0xffffffff;
    const int WARP_SIZE = 32;
    #pragma unroll
    for (int offset = WARP_SIZE/2; offset > 0; offset /= 2) {
        thread_sum += __shfl_down_sync(FULL_WARP_MASK, thread_sum, offset);
    }

    // Only the first thread in each warp writes to shared memory
    __shared__ double warp_sums[8];  // For 256 threads = 8 warps
    int warp_id = threadIdx.x / 32;
    int lane_id = threadIdx.x % 32;
    
    if (lane_id == 0) {
        warp_sums[warp_id] = thread_sum;
    }
    
    // Single sync point needed here for shared memory consistency
    __syncthreads();

    // Final reduction by first warp only
    if (threadIdx.x < 8) {
        double sum = warp_sums[threadIdx.x];
        
        // Warp-level reduction of final sums (no sync needed)
        #pragma unroll
        for (int offset = 4; offset > 0; offset /= 2) {
            sum += __shfl_down_sync(0xff, sum, offset);
        }

        if (threadIdx.x == 0) {
            atomicAdd(sum_out, sum);
        }
    }
}

torch::Tensor forward(torch::Tensor predictions, torch::Tensor targets) {
    TORCH_CHECK(predictions.is_cuda(), "predictions must be a CUDA tensor");
    TORCH_CHECK(targets.is_cuda(), "targets must be a CUDA tensor");
    TORCH_CHECK(predictions.numel() == targets.numel(),
                "predictions and targets must have the same number of elements");

    const int64_t num_elements = predictions.numel();
    auto accumulator = torch::zeros({1}, predictions.options().dtype(at::kDouble));

    const int grid_size = std::min(1024, (int)((num_elements + BLOCK_SIZE - 1) / BLOCK_SIZE));

    AT_DISPATCH_FLOATING_TYPES(predictions.scalar_type(), "mse_forward_cuda", ([&] {
        mse_forward_kernel_min_sync<scalar_t><<<grid_size, BLOCK_SIZE>>>(
            predictions.data_ptr<scalar_t>(),
            targets.data_ptr<scalar_t>(),
            accumulator.data_ptr<double>(),
            num_elements
        );
    }));

    auto result = accumulator.div_(static_cast<double>(num_elements));
    return result.to(predictions.dtype());
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &forward, "MSE forward (CUDA) with minimal synchronization");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 1.482 inst/cycle 0.002 5
Executed Ipc Elapsed 0.734 inst/cycle 0.000 5
Issue Slots Busy 38.214 % 1.356 5
Issued Ipc Active 1.530 inst/cycle 0.002 5
SM Busy 38.214 % 1.356 5
Memory Throughput 760239728635.412 byte/second 20145496554251018240.000 5
Mem Busy 13.774 % 0.009 5
Max Bandwidth 22.806 % 0.017 5
L1/TEX Hit Rate 0.000 % 0.000 5
L2 Hit Rate 18.908 % 0.012 5
Mem Pipes Busy 12.748 % 0.007 5
Warp Cycles Per Issued Instruction 32.114 cycle 0.066 5
Warp Cycles Per Executed Instruction 33.122 cycle 0.070 5
Avg. Active Threads Per Warp 31.380 0.000 5
Avg. Not Predicated Off Threads Per Warp 23.010 0.000 5
Max Active Clusters 0.000 cluster 0.000 5
Max Cluster Size 8.000 block 0.000 5
Overall GPU Occupancy 0.000 % 0.000 5
Cluster Occupancy 0.000 % 0.000 5
Block Limit SM 32.000 block 0.000 5
Block Limit Registers 8.000 block 0.000 5
Block Limit Shared Mem 28.000 block 0.000 5
Block Limit Warps 8.000 block 0.000 5
Theoretical Active Warps per SM 64.000 warp 0.000 5
Theoretical Occupancy 100.000 % 0.000 5
Achieved Occupancy 78.502 % 0.417 5
Achieved Active Warps Per SM 50.240 warp 0.169 5
Analysis Rules
Rule Description
INF HighPipeUtilization ALU is the highest-utilized pipeline (23.8%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN ThreadDivergence Instructions are executed in warps, which are groups of 32 threads. Optimal instruction throughput is achieved if all 32 threads of a warp execute the same instruction. The chosen launch configuration, early thread completion, and divergent flow control can significantly lower the number of active threads in a warp per cycle. This kernel achieves an average of 31.4 threads being active per cycle. This is further reduced to 23.0 threads per warp due to predication. The compiler may use predication to avoid an actual branch. Instead, all instructions are scheduled, but a per-thread condition code or predicate controls which threads execute the instructions. Try to avoid different execution paths within a warp when possible. In addition, ensure your kernel makes use of Independent Thread Scheduling, which allows a warp to reconverge after a data-dependent conditional block by explicitly calling __syncwarp().
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (77.8%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
Operation / Metric Value Unit
aten::to
CPU Time 1241167.01 μs
Device Time 229827.73 μs
Self CPU Time 50071.26 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 1191095.74 μs
Device Time 229827.73 μs
Self CPU Time 209047.03 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 4329787.72 μs
Device Time 6791325.75 μs
Self CPU Time 245532.32 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 4084257.44 μs
Device Time 6791325.75 μs
Self CPU Time 355151.43 μs
Self Device Time 6791244.70 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaLaunchKernel
CPU Time 4723727.41 μs
Device Time 521185.13 μs
Self CPU Time 4723727.41 μs
Self Device Time 521185.13 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void mse_forward_kernel_min_sync<float>(float const*, float const*, double*, long)
CPU Time 0.00 μs
Device Time 423924.05 μs
Self CPU Time 0.00 μs
Self Device Time 423924.05 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 6587212.20 μs
Self CPU Time 0.00 μs
Self Device Time 6587212.20 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Failed 
45249 warnings and 2 errors generated when compiling for host.
Error while processing /home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu.
Suppressed 45286 warnings (45239 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
Found compiler error(s).
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:24:24 bugprone-narrowing-conversions
24 | for (int idx = blockIdx.x * blockDim.x + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:26:21: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
26 | idx += blockDim.x * gridDim.x) {
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:27:31: error: no matching function for call to '__ldcg' [clang-diagnostic-error]
27 | float2 pred_vec = __ldcg(&preds2[idx]); // Cache hint for global loads
| ^~~~~~
/usr/local/cuda/include/cuda_bf16.hpp:1662:35: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __nv_bfloat162 *const' for 1st argument
1662 | __CUDA_BF16_DECL__ __nv_bfloat162 __ldcg(const __nv_bfloat162 *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/local/cuda/include/cuda_bf16.hpp:1668:34: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __nv_bfloat16 *const' for 1st argument
1668 | __CUDA_BF16_DECL__ __nv_bfloat16 __ldcg(const __nv_bfloat16 *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/local/cuda/include/cuda_fp16.hpp:1688:28: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __half2 *const' for 1st argument
1688 | __CUDA_FP16_DECL__ __half2 __ldcg(const __half2 *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/local/cuda/include/cuda_fp16.hpp:1694:27: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __half *const' for 1st argument
1694 | __CUDA_FP16_DECL__ __half __ldcg(const __half *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:28:30: error: no matching function for call to '__ldcg' [clang-diagnostic-error]
28 | float2 tgt_vec = __ldcg(&tgts2[idx]);
| ^~~~~~
/usr/local/cuda/include/cuda_bf16.hpp:1662:35: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __nv_bfloat162 *const' for 1st argument
1662 | __CUDA_BF16_DECL__ __nv_bfloat162 __ldcg(const __nv_bfloat162 *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/local/cuda/include/cuda_bf16.hpp:1668:34: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __nv_bfloat16 *const' for 1st argument
1668 | __CUDA_BF16_DECL__ __nv_bfloat16 __ldcg(const __nv_bfloat16 *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/local/cuda/include/cuda_fp16.hpp:1688:28: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __half2 *const' for 1st argument
1688 | __CUDA_FP16_DECL__ __half2 __ldcg(const __half2 *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~~~
/usr/local/cuda/include/cuda_fp16.hpp:1694:27: note: candidate function not viable: no known conversion from 'const float2 *' to 'const __half *const' for 1st argument
1694 | __CUDA_FP16_DECL__ __half __ldcg(const __half *const ptr)
| ^ ~~~~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:37:28: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
37 | int last_idx = num_elements - 1;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:43:24: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
43 | for (int idx = blockIdx.x * blockDim.x + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:45:21: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
45 | idx += blockDim.x * gridDim.x) {
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:61:19: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
61 | int warp_id = threadIdx.x / 32;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:62:19: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
62 | int lane_id = threadIdx.x % 32;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250208_optimize_b5_s4_e1_sweep/level_1/task_94/b5_s3_mse_min_sync/edit_1/edit_1.cu:98:5: warning: inside a lambda, '__func__' expands to the name of the function call operator; consider capturing the name of the enclosing function explicitly [bugprone-lambda-function-name]
98 | AT_DISPATCH_FLOATING_TYPES(predictions.scalar_type(), "mse_forward_cuda", ([&] {
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:237:34: note: expanded from macro 'AT_DISPATCH_FLOATING_TYPES'
237 | AT_DISPATCH_SWITCH(TYPE, NAME, AT_DISPATCH_CASE_FLOATING_TYPES(__VA_ARGS__))
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:233:3: note: expanded from macro 'AT_DISPATCH_CASE_FLOATING_TYPES'
233 | AT_DISPATCH_CASE(at::ScalarType::Double, __VA_ARGS__) \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:74:3: note: expanded from macro 'AT_DISPATCH_CASE'
74 | AT_PRIVATE_CASE_TYPE_USING_HINT(enum_type, scalar_t, __VA_ARGS__)
| ^
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:58:7: note: expanded from macro 'AT_PRIVATE_CHECK_SELECTIVE_BUILD'
58 | AT_ERROR( \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:711:32: note: expanded from macro 'AT_ERROR'
711 | C10_EXPAND_MSVC_WORKAROUND(TORCH_CHECK(false, ::c10::str(__VA_ARGS__))); \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:536:9: note: expanded from macro 'TORCH_CHECK'
536 | __func__, \
| ^