44_ConvTranspose2d_Multiply_GlobalAvgPool_GlobalAvgPool_Mean
• block_size_experimentation_base
import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
stride: int,
padding: int,
output_padding: int,
conv_transpose: torch.Tensor,
conv_transpose_bias: torch.Tensor,
multiplier: float,
) -> torch.Tensor:
"""
Applies transposed convolution, scalar multiplication, and multiple global average pooling operations.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width)
stride (int): Stride of the transposed convolution
padding (int): Padding of the transposed convolution
output_padding (int): Additional size added to output shape
conv_transpose (torch.Tensor): Transposed convolution weight tensor
conv_transpose_bias (torch.Tensor): Bias tensor for transposed convolution
multiplier (float): Scalar multiplier value
Returns:
torch.Tensor: Scalar output after applying operations
"""
x = F.conv_transpose2d(
x,
conv_transpose,
bias=conv_transpose_bias,
stride=stride,
padding=padding,
output_padding=output_padding,
)
x = x * multiplier
x = torch.mean(x, dim=[2, 3], keepdim=True)
x = torch.mean(x, dim=[2, 3], keepdim=True)
x = torch.mean(x)
return x
class Model(nn.Module):
"""
Model that performs a transposed convolution, multiplies by a scalar, applies global average pooling,
another global average pooling, and then calculates the mean.
"""
def __init__(
self,
in_channels,
out_channels,
kernel_size,
stride,
padding,
output_padding,
multiplier,
):
super(Model, self).__init__()
conv = nn.ConvTranspose2d(
in_channels,
out_channels,
kernel_size,
stride=stride,
padding=padding,
output_padding=output_padding,
)
self.conv_transpose_parameter = nn.Parameter(conv.weight)
self.conv_transpose_bias = nn.Parameter(
conv.bias
+ torch.randn(
conv.bias.shape, device=conv.bias.device, dtype=conv.bias.dtype
)
* 0.02
)
self.multiplier = multiplier
def forward(self, x, stride, padding, output_padding, fn=module_fn):
return fn(
x,
stride,
padding,
output_padding,
self.conv_transpose_parameter,
self.conv_transpose_bias,
self.multiplier,
)
batch_size = 128
in_channels = 3
out_channels = 16
height, width = 32, 32
kernel_size = 3
stride = 2
padding = 1
output_padding = 1
multiplier = 0.5
def get_inputs():
return [
torch.randn(batch_size, in_channels, height, width),
stride,
padding,
output_padding,
]
def get_init_inputs():
return [
in_channels,
out_channels,
kernel_size,
stride,
padding,
output_padding,
multiplier,
]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Model that performs a transposed convolution, multiplies by a scalar, applies global average pooling,
another global average pooling, and then calculates the mean.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride, padding, output_padding, multiplier):
super(Model, self).__init__()
self.conv_transpose = nn.ConvTranspose2d(in_channels, out_channels, kernel_size, stride=stride, padding=padding, output_padding=output_padding)
self.conv_transpose.bias = nn.Parameter(self.conv_transpose.bias + torch.randn(self.conv_transpose.bias.shape, device=self.conv_transpose.bias.device, dtype=self.conv_transpose.bias.dtype) * 0.02)
self.multiplier = multiplier
def forward(self, x):
x = self.conv_transpose(x)
x = x * self.multiplier
x = torch.mean(x, dim=[2, 3], keepdim=True) # First global average pooling
x = torch.mean(x, dim=[2, 3], keepdim=True) # Second global average pooling
x = torch.mean(x)
return x
batch_size = 128
in_channels = 3
out_channels = 16
height, width = 32, 32
kernel_size = 3
stride = 2
padding = 1
output_padding = 1
multiplier = 0.5
def get_inputs():
return [torch.randn(batch_size, in_channels, height, width)]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding, output_padding, multiplier]
Operation Name | 44_ConvTranspose2d_Multiply_GlobalAvgPool_GlobalAvgPool_Mean |
Level ID | 2 |
Task ID | 44 |
Kernel Name | block_size_experimentation_base |
CUDA Speedup (Native) | 1.107x |
CUDA Speedup (Compile) | 0.659x |
CUDA Runtime | 0.202 ms |
PyTorch Runtime (Native) | 0.224 ms |
PyTorch Runtime (Compile) | 0.133 ms |
Correct | True |
Max Diff (vs. Reference) | 0.000000 |
Model | azure-gpt-4o-2024-08-06 |
Temperature | 0.00 |
#include <torch/extension.h>
#include <ATen/ATen.h>
#include <cuda.h>
#include <cuda_runtime.h>
// Kernel to compute the mean of each (batch, channel) slice using vectorized loads,
// and manual loop unrolling via #pragma unroll to reduce loop overhead in both global memory
// accesses and shared memory reduction.
// Each block processes one (batch, channel) slice and atomically accumulates its slice mean
// into a global accumulator.
// Experimenting with different block sizes to find the optimal configuration.
// Template parameter for block size
template <unsigned int blockSize>
__global__ void block_size_experimentation_kernel(
const float* __restrict__ input,
float* __restrict__ global_accum,
int H,
int W,
int C
) {
extern __shared__ float shared[]; // Shared memory for reduction
int num_elements = H * W;
int batch = blockIdx.x / C;
int channel = blockIdx.x % C;
int input_offset = (batch * C + channel) * num_elements;
float sum = 0.0f;
// Use vectorized loads if the number of elements is divisible by 4 (ensuring 128-bit alignment)
if ((num_elements & 3) == 0) {
int num_vec = num_elements >> 2; // equivalent to num_elements / 4
const float4* in_vec = reinterpret_cast<const float4*>(input + input_offset);
for (int i = threadIdx.x; i < num_vec; i += blockDim.x) {
#pragma unroll
{
float4 v = __ldg(&in_vec[i]);
sum += v.x + v.y + v.z + v.w;
}
}
} else {
for (int i = threadIdx.x; i < num_elements; i += blockDim.x) {
#pragma unroll
{
sum += __ldg(&input[input_offset + i]);
}
}
}
// Store the partial sum in shared memory
shared[threadIdx.x] = sum;
__syncthreads();
// Intra-block reduction with manual unrolling
if (blockSize >= 512) {
if (threadIdx.x < 256)
shared[threadIdx.x] += shared[threadIdx.x + 256];
__syncthreads();
}
if (blockSize >= 256) {
if (threadIdx.x < 128)
shared[threadIdx.x] += shared[threadIdx.x + 128];
__syncthreads();
}
if (blockSize >= 128) {
if (threadIdx.x < 64)
shared[threadIdx.x] += shared[threadIdx.x + 64];
__syncthreads();
}
if (threadIdx.x < 32) {
volatile float* vsmem = shared;
#pragma unroll
for (int offset = 32; offset > 0; offset /= 2) {
vsmem[threadIdx.x] += vsmem[threadIdx.x + offset];
}
}
// Thread 0 computes the mean for this slice and atomically adds it to the global accumulator
if (threadIdx.x == 0) {
float slice_mean = shared[0] / static_cast<float>(num_elements);
atomicAdd(global_accum, slice_mean);
}
}
at::Tensor module_fn(
at::Tensor x,
int64_t stride,
int64_t padding,
int64_t output_padding,
at::Tensor conv_transpose,
at::Tensor conv_transpose_bias,
double multiplier
) {
// Perform transposed convolution using PyTorch's native function
at::Tensor y = at::conv_transpose2d(
x,
conv_transpose,
conv_transpose_bias,
{stride, stride},
{padding, padding},
{output_padding, output_padding},
1,
{1, 1}
);
// Scale the output
y = y * multiplier;
// Get dimensions (N, C, H, W)
auto dims = y.sizes();
int N = dims[0];
int C = dims[1];
int H = dims[2];
int W = dims[3];
// Allocate a scalar accumulator on the device and initialize to zero
auto options = torch::TensorOptions().device(y.device()).dtype(y.dtype());
at::Tensor accum = torch::zeros({1}, options);
// Launch one block per (batch, channel) slice
// Experiment with different block sizes
constexpr int blockSize = 128; // Example block size, can be changed to 32, 64, 256, 512
int numBlocks = N * C;
size_t sharedMemSize = blockSize * sizeof(float);
block_size_experimentation_kernel<blockSize><<<numBlocks, blockSize, sharedMemSize>>>(
y.data_ptr<float>(),
accum.data_ptr<float>(),
H, W, C
);
// Compute the final overall mean: average the means of all (batch, channel) slices
accum = accum / static_cast<float>(N * C);
return accum;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &module_fn, "Module function");
}
Metric | Value | Unit | Variance | Samples |
---|---|---|---|---|
Executed Ipc Active | 0.388 | inst/cycle | 0.000 | 5 |
Executed Ipc Elapsed | 0.284 | inst/cycle | 0.000 | 5 |
Issue Slots Busy | 9.754 | % | 0.001 | 5 |
Issued Ipc Active | 0.390 | inst/cycle | 0.000 | 5 |
SM Busy | 9.754 | % | 0.001 | 5 |
Memory Throughput | 2139097777115.080 | byte/second | 2539799648032197181440.000 | 5 |
Mem Busy | 35.982 | % | 0.766 | 5 |
Max Bandwidth | 63.968 | % | 2.415 | 5 |
L1/TEX Hit Rate | 0.000 | % | 0.000 | 5 |
L2 Hit Rate | 2.934 | % | 0.001 | 5 |
Mem Pipes Busy | 4.336 | % | 0.012 | 5 |
Warp Cycles Per Issued Instruction | 146.026 | cycle | 19.036 | 5 |
Warp Cycles Per Executed Instruction | 147.460 | cycle | 19.414 | 5 |
Avg. Active Threads Per Warp | 31.540 | 0.000 | 5 | |
Avg. Not Predicated Off Threads Per Warp | 30.380 | 0.000 | 5 | |
Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
Max Cluster Size | 8.000 | block | 0.000 | 5 |
Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
Cluster Occupancy | 0.000 | % | 0.000 | 5 |
Block Limit SM | 32.000 | block | 0.000 | 5 |
Block Limit Registers | 32.000 | block | 0.000 | 5 |
Block Limit Shared Mem | 42.000 | block | 0.000 | 5 |
Block Limit Warps | 16.000 | block | 0.000 | 5 |
Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
Achieved Occupancy | 87.868 | % | 0.057 | 5 |
Achieved Active Warps Per SM | 56.236 | warp | 0.023 | 5 |
Rule | Description |
---|---|
WRN HighPipeUtilization | All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details. |
INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (88.2%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
Operation / Metric | Value | Unit |
---|---|---|
aten::conv_transpose2d | ||
CPU Time | 5133983.55 | μs |
Device Time | 5056783.15 | μs |
Self CPU Time | 57878.11 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::convolution | ||
CPU Time | 5076105.44 | μs |
Device Time | 5056783.15 | μs |
Self CPU Time | 72229.42 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::_convolution | ||
CPU Time | 5003876.02 | μs |
Device Time | 5056783.15 | μs |
Self CPU Time | 144314.72 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::cudnn_convolution_transpose | ||
CPU Time | 3969317.35 | μs |
Device Time | 4084992.20 | μs |
Self CPU Time | 871465.40 | μs |
Self Device Time | 4084992.20 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
cudaLaunchKernel | ||
CPU Time | 5419125.99 | μs |
Device Time | 51558.70 | μs |
Self CPU Time | 5419125.99 | μs |
Self Device Time | 51558.70 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::zero_ | ||
CPU Time | 2145275.94 | μs |
Device Time | 2525989.10 | μs |
Self CPU Time | 108191.63 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
45258 warnings and 2 errors generated when compiling for host. Error while processing /home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_2/task_44/b10_s1_block_size_experimentation/base/base.cu. Suppressed 45292 warnings (45245 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well. Found compiler error(s).