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54_Conv2d_Multiply_LeakyReLU_GELU • threadblock_3d_mapping_base

Level 2 • Task 54
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(
    x: torch.Tensor,
    conv_weight: torch.Tensor,
    conv_bias: torch.Tensor,
    multiplier: torch.Tensor,
) -> torch.Tensor:
    """
    Applies convolution, scalar multiplication, LeakyReLU and GELU.

    Args:
        x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width)
        conv_weight (torch.Tensor): Convolution weights of shape (out_channels, in_channels, kernel_size, kernel_size)
        conv_bias (torch.Tensor): Convolution bias of shape (out_channels)
        multiplier (torch.Tensor): Learnable scalar of shape (out_channels, 1, 1)

    Returns:
        torch.Tensor: Output tensor after applying convolution, multiplication, LeakyReLU and GELU
    """
    x = F.conv2d(x, conv_weight, bias=conv_bias)
    x = x * multiplier
    x = F.leaky_relu(x)
    x = F.gelu(x)
    return x


class Model(nn.Module):
    """
    Model that performs a convolution, multiplies by a learnable scalar, applies LeakyReLU, and then GELU.
    """

    def __init__(self, in_channels, out_channels, kernel_size, multiplier_shape):
        super(Model, self).__init__()
        conv = nn.Conv2d(in_channels, out_channels, kernel_size)
        self.conv_weight = nn.Parameter(conv.weight)
        self.conv_bias = nn.Parameter(conv.bias)
        self.multiplier = nn.Parameter(torch.randn(multiplier_shape) * 0.02)

    def forward(self, x, fn=module_fn):
        return fn(x, self.conv_weight, self.conv_bias, self.multiplier)


batch_size = 128
in_channels = 3
out_channels = 16
height, width = 32, 32
kernel_size = 3
multiplier_shape = (out_channels, 1, 1)


def get_inputs():
    return [torch.randn(batch_size, in_channels, height, width)]


def get_init_inputs():
    return [in_channels, out_channels, kernel_size, multiplier_shape]

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs a convolution, multiplies by a learnable scalar, applies LeakyReLU, and then GELU.
    """
    def __init__(self, in_channels, out_channels, kernel_size, multiplier_shape):
        super(Model, self).__init__()
        self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)
        self.multiplier = nn.Parameter(torch.randn(multiplier_shape) * 0.02) 
        self.leaky_relu = nn.LeakyReLU()

    def forward(self, x):
        x = self.conv(x)
        x = x * self.multiplier
        x = self.leaky_relu(x)
        x = torch.nn.functional.gelu(x)
        return x

batch_size = 128
in_channels = 3
out_channels = 16
height, width = 32, 32
kernel_size = 3
multiplier_shape = (out_channels, 1, 1)

def get_inputs():
    return [torch.randn(batch_size, in_channels, height, width)]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, multiplier_shape]
Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name 54_Conv2d_Multiply_LeakyReLU_GELU
Level ID 2
Task ID 54
Kernel Name threadblock_3d_mapping_base
CUDA Speedup (Native) 1.281x
CUDA Speedup (Compile) 1.440x
CUDA Runtime 0.039 ms
PyTorch Runtime (Native) 0.050 ms
PyTorch Runtime (Compile) 0.056 ms
Correct True
Max Diff (vs. Reference) 0.000000
Model o3-mini-2025-01-31
Temperature 1.00
View Experiment Progress Details

Related Kernels (Level 2, Task 54 • 54_Conv2d_Multiply_LeakyReLU_GELU)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 54_Conv2d_Multiply_LeakyReLU_GELU 0.04 1.28 1.44
🥇 balanced_workload_distribution_base 0.04 1.28 1.44
🥇 warp_divergence_optimized_base 0.04 1.28 1.44
🥇 optimized_block_size_128_base 0.04 1.28 1.44
🥇 optimized_convolution_with_tunable_blocksize_base 0.04 1.28 1.44
🥇 direct_3d_indexing_opt_base 0.04 1.28 1.44
🥇 direct_3d_indexing_base 0.04 1.28 1.44
🥇 unroll_loops_54conv_edit_1 0.04 1.28 1.44
🥇 dynamic_block_size_54conv_base 0.04 1.28 1.44
🥇 threadblock_3d_mapping_base 0.04 1.28 1.44
🥇 balanced_thread_distribution_base 0.04 1.28 1.44
🥇 branchless_no_divergence_54conv_base 0.04 1.28 1.44
🥇 modular_device_functions_base 0.04 1.28 1.44
🥇 tile_based_2d_indexing_base 0.04 1.28 1.44
15 combined_conv_act_base 0.04 1.25 1.40
15 optimized_stride_loop_base 0.04 1.25 1.40
15 unroll_loops_54conv_base 0.04 1.25 1.40
15 54_Conv2d_Multiply_LeakyReLU_GELU_warp_divergence_reduction_base 0.04 1.25 1.40
15 dynamic_block_size_54conv_edit_1 0.04 1.25 1.40
15 modular_device_functions_edit_1 0.04 1.25 1.40 
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
#include <cmath>
#include <stdio.h>

// Device function: GELU approximation
__device__ __forceinline__ float gelu(float x) {
    const float k0 = 0.7978845608028654f; // sqrt(2/pi)
    return 0.5f * x * (1.0f + tanhf(k0 * (x + 0.044715f * x * x * x)));
}

// CUDA kernel using 3D grid mapping for output spatial and channel/batch dimensions
// Input tensor: [batch_size, in_channels, input_h, input_w]
// Weight tensor: [out_channels, in_channels, kernel_size, kernel_size]
// Bias: [out_channels]
// Multiplier: [out_channels]
// Output tensor: [batch_size, out_channels, output_h, output_w]
__global__ void conv_forward_kernel(
    const float* __restrict__ input,
    const float* __restrict__ weight,
    const float* __restrict__ bias,
    const float* __restrict__ multiplier,
    float* __restrict__ output,
    int batch_size,
    int in_channels,
    int input_h,
    int input_w,
    int out_channels,
    int kernel_size,
    int output_h,
    int output_w
) {
    // Map thread indices to output spatial location
    int ow = blockIdx.x * blockDim.x + threadIdx.x;
    int oh = blockIdx.y * blockDim.y + threadIdx.y;

    // Use gridDim.z to map the (batch, out_channel) dimensions
    int index = blockIdx.z;  // index in range [0, batch_size*out_channels)
    if (ow >= output_w || oh >= output_h) return;

    int oc = index % out_channels;
    int n  = index / out_channels;

    // Start with the bias value
    float sum = bias[oc];

    // Convolution: iterate over input channels and the kernel window
    for (int ic = 0; ic < in_channels; ic++) {
        // Precompute base indices for input and weight
        int input_base = (n * in_channels + ic) * input_h * input_w;
        int weight_base = ((oc * in_channels + ic) * kernel_size) * kernel_size;
        for (int i = 0; i < kernel_size; i++) {
            for (int j = 0; j < kernel_size; j++) {
                int in_h = oh + i; // since stride=1 and no padding
                int in_w = ow + j;
                int input_index = input_base + in_h * input_w + in_w;
                int weight_index = weight_base + i * kernel_size + j;
                sum += input[input_index] * weight[weight_index];
            }
        }
    }

    // Multiply with channel-specific multiplier
    sum *= multiplier[oc];

    // Apply LeakyReLU activation (negative slope = 0.01)
    sum = (sum > 0.0f) ? sum : 0.01f * sum;

    // Apply GELU activation
    float out_val = gelu(sum);

    // Calculate output index: output shape [batch_size, out_channels, output_h, output_w]
    int out_index = ((n * out_channels + oc) * output_h + oh) * output_w + ow;
    output[out_index] = out_val;
}

// C++ interface (to be called from Python)
torch::Tensor forward_cuda(
    torch::Tensor input,
    torch::Tensor conv_weight,
    torch::Tensor conv_bias,
    torch::Tensor multiplier
) {
    // Get input dimensions
    const int batch_size = input.size(0);
    const int in_channels = input.size(1);
    const int input_h = input.size(2);
    const int input_w = input.size(3);
    
    // Get convolution parameters
    const int out_channels = conv_weight.size(0);
    const int kernel_size = conv_weight.size(2);
    const int output_h = input_h - kernel_size + 1;
    const int output_w = input_w - kernel_size + 1;
    
    // Allocate output tensor
    auto output = torch::empty({batch_size, out_channels, output_h, output_w}, input.options());
    
    // Define block and grid dimensions
    // Block: 16x16 threads for spatial dimensions
    dim3 block(16, 16);
    // Grid.x covers width, Grid.y covers height, Grid.z covers (batch_size * out_channels)
    dim3 grid((output_w + block.x - 1) / block.x,
              (output_h + block.y - 1) / block.y,
              batch_size * out_channels);

    // Launch the CUDA kernel
    conv_forward_kernel<<<grid, block>>>(
        input.data_ptr<float>(),
        conv_weight.data_ptr<float>(),
        conv_bias.data_ptr<float>(),
        multiplier.data_ptr<float>(),
        output.data_ptr<float>(),
        batch_size,
        in_channels,
        input_h,
        input_w,
        out_channels,
        kernel_size,
        output_h,
        output_w
    );
    
    // Check for kernel errors
    cudaError_t err = cudaGetLastError();
    if (err != cudaSuccess) {
        printf("CUDA kernel failed: %s\n", cudaGetErrorString(err));
    }
    
    return output;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &forward_cuda, "Convolution, scalar multiplication, LeakyReLU and GELU (CUDA) with 3D thread mapping");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 3.018 inst/cycle 0.000 5
Executed Ipc Elapsed 2.796 inst/cycle 0.000 5
Issue Slots Busy 75.618 % 0.049 5
Issued Ipc Active 3.026 inst/cycle 0.000 5
SM Busy 75.618 % 0.049 5
Memory Throughput 36487428276.926 byte/second 31768610782035464.000 5
Mem Busy 61.154 % 0.070 5
Max Bandwidth 41.656 % 0.033 5
L1/TEX Hit Rate 87.238 % 0.000 5
L2 Hit Rate 92.754 % 0.030 5
Mem Pipes Busy 55.040 % 0.055 5
Warp Cycles Per Issued Instruction 16.430 cycle 0.002 5
Warp Cycles Per Executed Instruction 16.458 cycle 0.002 5
Avg. Active Threads Per Warp 30.070 0.000 5
Avg. Not Predicated Off Threads Per Warp 27.920 0.000 5
Max Active Clusters 0.000 cluster 0.000 5
Max Cluster Size 8.000 block 0.000 5
Overall GPU Occupancy 0.000 % 0.000 5
Cluster Occupancy 0.000 % 0.000 5
Block Limit SM 32.000 block 0.000 5
Block Limit Registers 8.000 block 0.000 5
Block Limit Shared Mem 32.000 block 0.000 5
Block Limit Warps 8.000 block 0.000 5
Theoretical Active Warps per SM 64.000 warp 0.000 5
Theoretical Occupancy 100.000 % 0.000 5
Achieved Occupancy 77.796 % 0.033 5
Achieved Active Warps Per SM 49.788 warp 0.014 5
Analysis Rules
Rule Description
INF HighPipeUtilization ALU is the highest-utilized pipeline (38.1%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (78.0%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
Operation / Metric Value Unit
aten::to
CPU Time 189624.83 μs
Device Time 82.08 μs
Self CPU Time 57.74 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 189567.09 μs
Device Time 82.08 μs
Self CPU Time 124.71 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::empty_strided
CPU Time 189094.20 μs
Device Time 0.00 μs
Self CPU Time 133.74 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaDeviceGetStreamPriorityRange
CPU Time 188565.08 μs
Device Time 0.00 μs
Self CPU Time 188565.08 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaLaunchKernel
CPU Time 411651.23 μs
Device Time 10020.33 μs
Self CPU Time 411651.23 μs
Self Device Time 10020.33 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
conv_forward_kernel(float const*, float const*, float const*, float const*, float*, int, int, int, int, int, int, int, int)
CPU Time 0.00 μs
Device Time 179053.73 μs
Self CPU Time 0.00 μs
Self Device Time 179053.73 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaEventRecord
CPU Time 13306.61 μs
Device Time 19973.53 μs
Self CPU Time 13306.61 μs
Self Device Time 19973.53 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 148743.30 μs
Device Time 387836.27 μs
Self CPU Time 9149.22 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 139595.75 μs
Device Time 387836.27 μs
Self CPU Time 12240.82 μs
Self Device Time 387836.27 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 387836.27 μs
Self CPU Time 0.00 μs
Self Device Time 387836.27 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Completed 
45293 warnings generated when compiling for host.
Suppressed 45324 warnings (45277 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:22:5 bugprone-easily-swappable-parameters
22 | const float* __restrict__ weight,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
23 | const float* __restrict__ bias,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
24 | const float* __restrict__ multiplier,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:22:31: note: the first parameter in the range is 'weight'
22 | const float* __restrict__ weight,
| ^~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:24:31: note: the last parameter in the range is 'multiplier'
24 | const float* __restrict__ multiplier,
| ^~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:26:5: warning: 2 adjacent parameters of 'conv_forward_kernel' of similar type ('int') are easily swapped by mistake [bugprone-easily-swappable-parameters]
26 | int batch_size,
| ^~~~~~~~~~~~~~~
27 | int in_channels,
| ~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:26:9: note: the first parameter in the range is 'batch_size'
26 | int batch_size,
| ^~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:27:9: note: the last parameter in the range is 'in_channels'
27 | int in_channels,
| ^~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:29:5: warning: 3 adjacent parameters of 'conv_forward_kernel' of similar type ('int') are easily swapped by mistake [bugprone-easily-swappable-parameters]
29 | int input_w,
| ^~~~~~~~~~~~
30 | int out_channels,
| ~~~~~~~~~~~~~~~~~
31 | int kernel_size,
| ~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:29:9: note: the first parameter in the range is 'input_w'
29 | int input_w,
| ^~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:31:9: note: the last parameter in the range is 'kernel_size'
31 | int kernel_size,
| ^~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:36:14: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
36 | int ow = blockIdx.x * blockDim.x + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:37:14: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
37 | int oh = blockIdx.y * blockDim.y + threadIdx.y;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:40:17: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
40 | int index = blockIdx.z; // index in range [0, batch_size*out_channels)
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:81:19: warning: the parameter 'input' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
81 | torch::Tensor input,
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:82:19: warning: the parameter 'conv_weight' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
82 | torch::Tensor conv_weight,
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:83:19: warning: the parameter 'conv_bias' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
83 | torch::Tensor conv_bias,
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:84:19: warning: the parameter 'multiplier' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
84 | torch::Tensor multiplier
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:87:28: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
87 | const int batch_size = input.size(0);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:88:29: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
88 | const int in_channels = input.size(1);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:89:25: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
89 | const int input_h = input.size(2);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:90:25: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
90 | const int input_w = input.size(3);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:93:30: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
93 | const int out_channels = conv_weight.size(0);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_2/task_54/b3_s1_threadblock_3d_mapping/base/base.cu:94:29: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
94 | const int kernel_size = conv_weight.size(2);
| ^