← Back to Leaderboard

The AI CUDA Engineer 👷

27_SELU_ • 27_selu_aligned_ldg_base

Level 1 • Task 27
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(x: torch.Tensor) -> torch.Tensor:
    """
    Applies SELU activation to the input tensor.

    Args:
        x (torch.Tensor): Input tensor of any shape.

    Returns:
        torch.Tensor: Output tensor with SELU applied, same shape as input.
    """
    return F.selu(x)


class Model(nn.Module):
    """
    Simple model that performs a SELU activation.
    """

    def __init__(self):
        super(Model, self).__init__()

    def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
        return fn(x)


batch_size = 16
dim = 16384


def get_inputs():
    x = torch.randn(batch_size, dim)
    return [x]


def get_init_inputs():
    return []  # No special initialization inputs needed

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Simple model that performs a SELU activation.
    """
    def __init__(self):
        super(Model, self).__init__()
    
    def forward(self, x: torch.Tensor) -> torch.Tensor:
        """
        Applies SELU activation to the input tensor.

        Args:
            x (torch.Tensor): Input tensor of any shape.

        Returns:
            torch.Tensor: Output tensor with SELU applied, same shape as input.
        """
        return torch.selu(x)

batch_size = 16
dim = 16384

def get_inputs():
    x = torch.randn(batch_size, dim)
    return [x]

def get_init_inputs():
    return []  # No special initialization inputs needed
Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name 27_SELU_
Level ID 1
Task ID 27
Kernel Name 27_selu_aligned_ldg_base
CUDA Speedup (Native) 1.099x
CUDA Speedup (Compile) 4.963x
CUDA Runtime 0.006 ms
PyTorch Runtime (Native) 0.007 ms
PyTorch Runtime (Compile) 0.030 ms
Correct True
Max Diff (vs. Reference) 0.000000
Model bedrock/anthropic.claude-3-5-sonnet-20241022-v2:0
Temperature 0.50
View Experiment Progress Details

Related Kernels (Level 1, Task 27 • 27_SELU_)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 selu_vectorized_base_base 0.01 1.10 4.96
🥇 selu_shared_opt_base 0.01 1.10 4.96
🥇 27_selu_aligned_ldg_base 0.01 1.10 4.96
🥇 27_selu_aligned_ldg_edit_1 0.01 1.10 4.96
5 27_selu_unroll_optimized_base 0.01 0.94 4.25
5 27_SELU_ 0.01 0.94 4.25
5 selu_kernel_combined_optimized_base 0.01 0.94 4.25
5 selu_atomic_optimized_base 0.01 0.94 4.25
5 27_selu_manual_unroll_base 0.01 0.94 4.25
5 modular_selu_optimized_base 0.01 0.94 4.25
5 selu_2d_indexing_base 0.01 0.94 4.25
5 selu_shared_mem_optimized_base 0.01 0.94 4.25
5 selu_kernel_combined_base 0.01 0.94 4.25
5 evenly_distributed_selu_base 0.01 0.94 4.25
5 selu_memory_coalesced_base_base 0.01 0.94 4.25
5 evenly_partitioned_selu_base 0.01 0.94 4.25
5 selu_even_load_balance_base 0.01 0.94 4.25
5 selu_atomic_minimal_base 0.01 0.94 4.25
5 selu_coalesced_access_base_base 0.01 0.94 4.25
5 27_selu_vectorized_base 0.01 0.94 4.25 
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>

template <typename scalar_t>
__device__ inline scalar_t my_exp(scalar_t x);

template <>
__device__ inline float my_exp<float>(float x) {
    return expf(x);
}

template <>
__device__ inline double my_exp<double>(double x) {
    return exp(x);
}

template <typename scalar_t>
__global__ void selu_kernel_aligned(const scalar_t* __restrict__ input,
                                  scalar_t* __restrict__ output,
                                  const size_t numel) {
    const scalar_t alpha = static_cast<scalar_t>(1.67326324235437728481);
    const scalar_t lambda = static_cast<scalar_t>(1.05070098735548049342);

    // Process 4 elements per thread for better memory coalescing
    const size_t idx_base = (blockIdx.x * blockDim.x + threadIdx.x) * 4;
    const size_t stride = blockDim.x * gridDim.x * 4;

    // Use vector types for aligned loads when possible
    if (std::is_same<scalar_t, float>::value && (reinterpret_cast<uintptr_t>(input) % 16 == 0)) {
        for (size_t i = idx_base; i < numel; i += stride) {
            float4 in_vec;
            float4 out_vec;
            
            if (i + 3 < numel) {
                // Load 4 elements at once using __ldg
                const float4* in_ptr4 = reinterpret_cast<const float4*>(input + i);
                in_vec = __ldg(in_ptr4);
                
                // Process each component
                out_vec.x = (in_vec.x > 0) ? in_vec.x : alpha * (my_exp(in_vec.x) - 1.0f);
                out_vec.y = (in_vec.y > 0) ? in_vec.y : alpha * (my_exp(in_vec.y) - 1.0f);
                out_vec.z = (in_vec.z > 0) ? in_vec.z : alpha * (my_exp(in_vec.z) - 1.0f);
                out_vec.w = (in_vec.w > 0) ? in_vec.w : alpha * (my_exp(in_vec.w) - 1.0f);
                
                // Apply lambda and store
                out_vec.x *= lambda;
                out_vec.y *= lambda;
                out_vec.z *= lambda;
                out_vec.w *= lambda;
                
                // Store 4 elements at once
                *reinterpret_cast<float4*>(output + i) = out_vec;
            } else {
                // Handle remaining elements
                for (size_t j = 0; j < 4 && i + j < numel; ++j) {
                    scalar_t x = __ldg(input + i + j);
                    scalar_t result = (x > static_cast<scalar_t>(0))
                                    ? x
                                    : alpha * (my_exp(x) - static_cast<scalar_t>(1));
                    output[i + j] = lambda * result;
                }
            }
        }
    } else {
        // Fallback for double or unaligned memory
        for (size_t i = idx_base; i < numel; i += stride) {
            for (size_t j = 0; j < 4 && i + j < numel; ++j) {
                scalar_t x = __ldg(input + i + j);
                scalar_t result = (x > static_cast<scalar_t>(0))
                                ? x
                                : alpha * (my_exp(x) - static_cast<scalar_t>(1));
                output[i + j] = lambda * result;
            }
        }
    }
}

torch::Tensor selu_forward(torch::Tensor input) {
    TORCH_CHECK(input.is_cuda(), "Input tensor must be a CUDA tensor");
    
    auto output = torch::empty_like(input);
    const size_t numel = input.numel();
    
    // Optimize block size for H100
    const int threads = 256;
    const int blocks = (numel + threads * 4 - 1) / (threads * 4);

    AT_DISPATCH_FLOATING_TYPES(input.scalar_type(), "selu_forward_cuda", ([&] {
        selu_kernel_aligned<scalar_t><<<blocks, threads>>>(
            input.data_ptr<scalar_t>(),
            output.data_ptr<scalar_t>(),
            numel
        );
    }));

    return output;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &selu_forward, "SELU Activation Forward (CUDA)");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 0.552 inst/cycle 0.000 4
Executed Ipc Elapsed 0.200 inst/cycle 0.000 4
Issue Slots Busy 14.925 % 0.016 4
Issued Ipc Active 0.600 inst/cycle 0.000 4
SM Busy 14.925 % 0.016 4
Memory Throughput 273528541016.332 byte/second 155906429711724511232.000 4
Mem Busy 12.890 % 0.392 4
Max Bandwidth 11.890 % 0.355 4
L1/TEX Hit Rate 0.000 % 0.000 4
L2 Hit Rate 67.710 % 0.049 4
Mem Pipes Busy 3.573 % 0.030 4
Warp Cycles Per Issued Instruction 22.290 cycle 0.049 4
Warp Cycles Per Executed Instruction 24.047 cycle 0.060 4
Avg. Active Threads Per Warp 32.000 0.000 4
Avg. Not Predicated Off Threads Per Warp 27.890 0.000 4
Max Active Clusters 0.000 cluster 0.000 4
Max Cluster Size 8.000 block 0.000 4
Overall GPU Occupancy 0.000 % 0.000 4
Cluster Occupancy 0.000 % 0.000 4
Block Limit SM 32.000 block 0.000 4
Block Limit Registers 8.000 block 0.000 4
Block Limit Shared Mem 32.000 block 0.000 4
Block Limit Warps 8.000 block 0.000 4
Theoretical Active Warps per SM 64.000 warp 0.000 4
Theoretical Occupancy 100.000 % 0.000 4
Achieved Occupancy 21.145 % 0.001 4
Achieved Active Warps Per SM 13.530 warp 0.001 4
Analysis Rules
Rule Description
WRN HighPipeUtilization All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (21.1%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
Operation / Metric Value Unit
aten::to
CPU Time 462032.37 μs
Device Time 40.00 μs
Self CPU Time 35.67 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 461996.70 μs
Device Time 40.00 μs
Self CPU Time 93.13 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::empty_strided
CPU Time 481167.72 μs
Device Time 0.00 μs
Self CPU Time 19613.12 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaDeviceGetStreamPriorityRange
CPU Time 461368.74 μs
Device Time 0.00 μs
Self CPU Time 461368.74 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaLaunchKernel
CPU Time 521788.60 μs
Device Time 23051.49 μs
Self CPU Time 521788.60 μs
Self Device Time 23051.49 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void selu_kernel_aligned<float>(float const*, float*, unsigned long)
CPU Time 0.00 μs
Device Time 32360.38 μs
Self CPU Time 0.00 μs
Self Device Time 32360.38 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaEventRecord
CPU Time 19863.54 μs
Device Time 44443.48 μs
Self CPU Time 19863.54 μs
Self Device Time 44443.48 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 64051.71 μs
Device Time 658084.40 μs
Self CPU Time 13622.17 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 50430.75 μs
Device Time 658084.40 μs
Self CPU Time 15762.35 μs
Self Device Time 658084.40 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 658084.40 μs
Self CPU Time 0.00 μs
Self Device Time 658084.40 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Completed 
45282 warnings generated when compiling for host.
Suppressed 45321 warnings (45274 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:27:29 bugprone-implicit-widening-of-multiplication-result
27 | const size_t idx_base = (blockIdx.x * blockDim.x + threadIdx.x) * 4;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:27:29: note: make conversion explicit to silence this warning
5 | const size_t idx_base = (blockIdx.x * blockDim.x + threadIdx.x) * 4;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| static_cast<const size_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:27:29: note: perform multiplication in a wider type
27 | const size_t idx_base = (blockIdx.x * blockDim.x + threadIdx.x) * 4;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| static_cast<const size_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:28:27: warning: performing an implicit widening conversion to type 'const size_t' (aka 'const unsigned long') of a multiplication performed in type 'unsigned int' [bugprone-implicit-widening-of-multiplication-result]
28 | const size_t stride = blockDim.x * gridDim.x * 4;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:28:27: note: make conversion explicit to silence this warning
28 | const size_t stride = blockDim.x * gridDim.x * 4;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
| static_cast<const size_t>()
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:28:27: note: perform multiplication in a wider type
28 | const size_t stride = blockDim.x * gridDim.x * 4;
| ^~~~~~~~~~~~~~~~~~~~~~
| static_cast<const size_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:24: warning: narrowing conversion from 'size_t' (aka 'unsigned long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:33: warning: performing an implicit widening conversion to type 'size_t' (aka 'unsigned long') of a multiplication performed in type 'int' [bugprone-implicit-widening-of-multiplication-result]
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:33: note: make conversion explicit to silence this warning
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^~~~~~~~~~~
| static_cast<size_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:33: note: perform multiplication in a wider type
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^~~~~~~
| static_cast<long>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:53: warning: performing an implicit widening conversion to type 'size_t' (aka 'unsigned long') of a multiplication performed in type 'int' [bugprone-implicit-widening-of-multiplication-result]
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:53: note: make conversion explicit to silence this warning
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^~~~~~~~~~~
| static_cast<size_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:88:53: note: perform multiplication in a wider type
88 | const int blocks = (numel + threads * 4 - 1) / (threads * 4);
| ^~~~~~~
| static_cast<long>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250212_optimize_b5_s4_e1_v2/level_1/task_27/b5_s2_27_selu_aligned_ldg/base/base.cu:90:5: warning: inside a lambda, '__func__' expands to the name of the function call operator; consider capturing the name of the enclosing function explicitly [bugprone-lambda-function-name]
90 | AT_DISPATCH_FLOATING_TYPES(input.scalar_type(), "selu_forward_cuda", ([&] {
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:237:34: note: expanded from macro 'AT_DISPATCH_FLOATING_TYPES'
237 | AT_DISPATCH_SWITCH(TYPE, NAME, AT_DISPATCH_CASE_FLOATING_TYPES(__VA_ARGS__))
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:233:3: note: expanded from macro 'AT_DISPATCH_CASE_FLOATING_TYPES'
233 | AT_DISPATCH_CASE(at::ScalarType::Double, __VA_ARGS__) \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:74:3: note: expanded from macro 'AT_DISPATCH_CASE'
74 | AT_PRIVATE_CASE_TYPE_USING_HINT(enum_type, scalar_t, __VA_ARGS__)
| ^
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:58:7: note: expanded from macro 'AT_PRIVATE_CHECK_SELECTIVE_BUILD'
58 | AT_ERROR( \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:711:32: note: expanded from macro 'AT_ERROR'
711 | C10_EXPAND_MSVC_WORKAROUND(TORCH_CHECK(false, ::c10::str(__VA_ARGS__))); \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:536:9: note: expanded from macro 'TORCH_CHECK'
536 | __func__, \
| ^