import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
kernel_size: int,
stride: int,
padding: int,
dilation: int,
return_indices: bool,
) -> torch.Tensor:
"""
Functional implementation of Max Pooling 1D.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, num_features, sequence_length).
kernel_size (int): Size of the window to take a max over.
stride (int): Stride of the window.
padding (int): Implicit zero padding to be added on both sides.
dilation (int): Spacing between kernel elements.
return_indices (bool): Whether to return the indices of the maximum values.
Returns:
torch.Tensor: Output tensor with Max Pooling 1D applied.
"""
return F.max_pool1d(
x,
kernel_size=kernel_size,
stride=stride,
padding=padding,
dilation=dilation,
return_indices=return_indices,
)
class Model(nn.Module):
"""
Simple model that performs Max Pooling 1D.
"""
def __init__(
self,
kernel_size: int,
stride: int,
padding: int,
dilation: int,
return_indices: bool,
):
"""
Initializes the Max Pooling 1D layer.
Args:
kernel_size (int): Size of the window to take a max over.
stride (int): Stride of the window.
padding (int): Implicit zero padding to be added on both sides.
dilation (int): Spacing between kernel elements.
return_indices (bool): Whether to return the indices of the maximum values.
"""
super(Model, self).__init__()
self.kernel_size = kernel_size
self.stride = stride
self.padding = padding
self.dilation = dilation
self.return_indices = return_indices
def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
"""
Applies Max Pooling 1D to the input tensor.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, num_features, sequence_length).
fn: Function to apply (defaults to module_fn)
Returns:
torch.Tensor: Output tensor with Max Pooling 1D applied.
"""
return fn(
x,
self.kernel_size,
self.stride,
self.padding,
self.dilation,
self.return_indices,
)
batch_size = 16
features = 64
sequence_length = 128
kernel_size = 4
stride = 2
padding = 2
dilation = 3
return_indices = False
def get_inputs():
x = torch.randn(batch_size, features, sequence_length)
return [x]
def get_init_inputs():
return [kernel_size, stride, padding, dilation, return_indices]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Simple model that performs Max Pooling 1D.
"""
def __init__(self, kernel_size: int, stride: int = None, padding: int = 0, dilation: int = 1, return_indices: bool = False):
"""
Initializes the Max Pooling 1D layer.
Args:
kernel_size (int): Size of the window to take a max over.
stride (int, optional): Stride of the window. Defaults to None (same as kernel_size).
padding (int, optional): Implicit zero padding to be added on both sides. Defaults to 0.
dilation (int, optional): Spacing between kernel elements. Defaults to 1.
return_indices (bool, optional): Whether to return the indices of the maximum values. Defaults to False.
"""
super(Model, self).__init__()
self.maxpool = nn.MaxPool1d(kernel_size=kernel_size, stride=stride, padding=padding, dilation=dilation, return_indices=return_indices)
def forward(self, x: torch.Tensor) -> torch.Tensor:
"""
Applies Max Pooling 1D to the input tensor.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, num_features, sequence_length).
Returns:
torch.Tensor: Output tensor with Max Pooling 1D applied, shape (batch_size, num_features, output_sequence_length).
"""
return self.maxpool(x)
batch_size = 16
features = 64
sequence_length = 128
kernel_size = 4
stride = 2
padding = 2
dilation = 3
return_indices = False
def get_inputs():
x = torch.randn(batch_size, features, sequence_length)
return [x]
def get_init_inputs():
return [kernel_size, stride, padding, dilation, return_indices]#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
// This kernel organizes threads so that each block processes contiguous output indices along the innermost dimension.
// Threads in the same warp will access consecutive memory locations in the output tensor, ensuring memory coalescing.
__global__ void max_pool1d_coalesced_aligned_kernel(
const float* __restrict__ input,
float* __restrict__ output,
int64_t* __restrict__ indices,
const int batch_size,
const int num_channels,
const int input_length,
const int kernel_size,
const int stride,
const int padding,
const int dilation,
const int output_length,
const bool return_indices) {
// Use a 2D grid: blockIdx.x covers output index dimension; blockIdx.y covers (b, c) combinations.
int i = blockIdx.x * blockDim.x + threadIdx.x; // output index in the innermost dimension
int row = blockIdx.y; // Flattened index for (batch, channel)
int b = row / num_channels;
int c = row % num_channels;
if (i >= output_length) return;
// Compute base pointer for the current batch and channel
const float* input_base = input + (b * num_channels * input_length + c * input_length);
int input_start = i * stride - padding;
float max_val = -INFINITY;
int max_idx = -1;
// Loop over the pooling window
for (int k = 0; k < kernel_size; ++k) {
int pos = input_start + k * dilation;
if (pos >= 0 && pos < input_length) {
float val = __ldg(input_base + pos);
if (val > max_val) {
max_val = val;
max_idx = pos;
}
}
}
// Compute the output index. Memory layout: [b, c, i] with i as the fastest dimension.
int out_index = b * (num_channels * output_length) + c * output_length + i;
output[out_index] = max_val;
if (return_indices)
indices[out_index] = max_idx;
}
// The forward function creates output tensors and launches the kernel with a 2D grid.
// Grid dimensions:
// - gridDim.x: covers the output_length dimension using blockDim.x threads
// - gridDim.y: covers the (batch, channel) combinations
torch::Tensor forward(
torch::Tensor x,
int64_t kernel_size,
int64_t stride,
int64_t padding,
int64_t dilation,
bool return_indices) {
TORCH_CHECK(x.dim() == 3, "Input must be a 3D tensor.");
TORCH_CHECK(x.is_cuda(), "Input tensor must be on CUDA.");
TORCH_CHECK(x.is_contiguous(), "Input tensor must be contiguous.");
const int batch_size = x.size(0);
const int num_channels = x.size(1);
const int input_length = x.size(2);
const int output_length = ((input_length + 2 * padding - dilation * (kernel_size - 1) - 1) / stride) + 1;
TORCH_CHECK(output_length > 0, "Output length must be positive.");
auto options = torch::TensorOptions().dtype(x.dtype()).device(x.device());
auto output = torch::empty({batch_size, num_channels, output_length}, options);
torch::Tensor indices;
if (return_indices) {
indices = torch::empty({batch_size, num_channels, output_length}, options.dtype(torch::kInt64));
}
// Configure a 2D grid: threads.x covers the contiguous 'i' dimension, threads in each block read/write consecutive
// memory locations, ensuring coalescing. Block dimension in y is implicitly 1.
const int threads_x = 256;
dim3 threads(threads_x);
dim3 blocks((output_length + threads_x - 1) / threads_x, batch_size * num_channels);
max_pool1d_coalesced_aligned_kernel<<<blocks, threads>>>(
x.data_ptr<float>(),
output.data_ptr<float>(),
return_indices ? indices.data_ptr<int64_t>() : nullptr,
batch_size,
num_channels,
input_length,
kernel_size,
stride,
padding,
dilation,
output_length,
return_indices
);
return return_indices ? torch::cat({output, indices}, -1) : output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &forward, "MaxPool1D forward with coalesced and aligned accesses (CUDA)");
}
| Metric | Value | Unit | Variance | Samples |
|---|---|---|---|---|
| Executed Ipc Active | 0.770 | inst/cycle | 0.000 | 5 |
| Executed Ipc Elapsed | 0.298 | inst/cycle | 0.000 | 5 |
| Issue Slots Busy | 21.702 | % | 0.039 | 5 |
| Issued Ipc Active | 0.868 | inst/cycle | 0.000 | 5 |
| SM Busy | 21.702 | % | 0.039 | 5 |
| Memory Throughput | 134136553042.824 | byte/second | 4306120113096010240.000 | 5 |
| Mem Busy | 10.384 | % | 0.038 | 5 |
| Max Bandwidth | 7.198 | % | 0.012 | 5 |
| L1/TEX Hit Rate | 69.170 | % | 0.001 | 5 |
| L2 Hit Rate | 71.638 | % | 0.068 | 5 |
| Mem Pipes Busy | 10.254 | % | 0.027 | 5 |
| Warp Cycles Per Issued Instruction | 37.308 | cycle | 14.840 | 5 |
| Warp Cycles Per Executed Instruction | 42.112 | cycle | 18.926 | 5 |
| Avg. Active Threads Per Warp | 31.270 | 0.000 | 5 | |
| Avg. Not Predicated Off Threads Per Warp | 30.140 | 0.000 | 5 | |
| Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
| Max Cluster Size | 8.000 | block | 0.000 | 5 |
| Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
| Cluster Occupancy | 0.000 | % | 0.000 | 5 |
| Block Limit SM | 32.000 | block | 0.000 | 5 |
| Block Limit Registers | 8.000 | block | 0.000 | 5 |
| Block Limit Shared Mem | 32.000 | block | 0.000 | 5 |
| Block Limit Warps | 8.000 | block | 0.000 | 5 |
| Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
| Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
| Achieved Occupancy | 48.730 | % | 0.297 | 5 |
| Achieved Active Warps Per SM | 31.186 | warp | 0.123 | 5 |
| Rule | Description |
|---|---|
| WRN HighPipeUtilization | All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details. |
| INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
| WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (48.4%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
| Operation / Metric | Value | Unit |
|---|---|---|
| aten::to | ||
| CPU Time | 586641.18 | μs |
| Device Time | 21.15 | μs |
| Self CPU Time | 37.47 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::_to_copy | ||
| CPU Time | 586603.70 | μs |
| Device Time | 21.15 | μs |
| Self CPU Time | 92.55 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::empty_strided | ||
| CPU Time | 586355.53 | μs |
| Device Time | 0.00 | μs |
| Self CPU Time | 80.65 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaDeviceGetStreamPriorityRange | ||
| CPU Time | 586094.70 | μs |
| Device Time | 0.00 | μs |
| Self CPU Time | 586094.70 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaLaunchKernel | ||
| CPU Time | 496763.53 | μs |
| Device Time | 23209.08 | μs |
| Self CPU Time | 496763.53 | μs |
| Self Device Time | 23209.08 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| max_pool1d_coalesced_aligned_kernel(float const*, float*, long*, int, int, int, int, int, int, int, int, bool) | ||
| CPU Time | 0.00 | μs |
| Device Time | 23489.02 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 23489.02 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaEventRecord | ||
| CPU Time | 19972.54 | μs |
| Device Time | 42935.22 | μs |
| Self CPU Time | 19972.54 | μs |
| Self Device Time | 42935.22 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zero_ | ||
| CPU Time | 64403.92 | μs |
| Device Time | 641017.91 | μs |
| Self CPU Time | 14782.79 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::fill_ | ||
| CPU Time | 49625.36 | μs |
| Device Time | 641017.91 | μs |
| Self CPU Time | 15775.05 | μs |
| Self Device Time | 641017.91 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>) | ||
| CPU Time | 0.00 | μs |
| Device Time | 641017.91 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 641017.91 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
45293 warnings generated when compiling for host. Suppressed 45326 warnings (45279 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.