← Back to Leaderboard

The AI CUDA Engineer 👷

6_Matmul_with_large_K_dimension_ • 6_matmul_modular_refactored_base

Level 1 • Task 6
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(A, B):
    """
    Performs a single matrix multiplication (C = A * B) with a large K dimension.

    Args:
        A: Input tensor of shape (M, K)
        B: Input tensor of shape (K, N)

    Returns:
        Output tensor of shape (M, N)
    """
    return torch.matmul(A, B)


class Model(nn.Module):
    """
    Simple model that performs a single matrix multiplication (C = A * B) with a large K dimension
    """

    def __init__(self):
        super(Model, self).__init__()

    def forward(self, A: torch.Tensor, B: torch.Tensor, fn=module_fn) -> torch.Tensor:
        return fn(A, B)


M = 256
N = 256
K = 131072


def get_inputs():
    A = torch.randn(M, K)
    B = torch.randn(K, N)
    return [A, B]


def get_init_inputs():
    return []  # No special initialization inputs needed

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Simple model that performs a single matrix multiplication (C = A * B) with a large K dimension
    """
    def __init__(self):
        super(Model, self).__init__()
    
    def forward(self, A: torch.Tensor, B: torch.Tensor) -> torch.Tensor:
        """
        Performs matrix multiplication of A and B.

        Args:
            A: Input tensor of shape (M, K)
            B: Input tensor of shape (K, N)

        Returns:
            Output tensor of shape (M, N)
        """
        return torch.matmul(A, B)

M = 256
N = 256
K = 131072

def get_inputs():
    A = torch.randn(M, K)
    B = torch.randn(K, N)
    return [A, B]

def get_init_inputs():
    return []  # No special initialization inputs needed
Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name 6_Matmul_with_large_K_dimension_
Level ID 1
Task ID 6
Kernel Name 6_matmul_modular_refactored_base
CUDA Speedup (Native) 0.065x
CUDA Speedup (Compile) 0.107x
CUDA Runtime 5.296 ms
PyTorch Runtime (Native) 0.343 ms
PyTorch Runtime (Compile) 0.568 ms
Correct True
Max Diff (vs. Reference) 0.005000
Model o3-mini-2025-01-31
Temperature 1.00
View Experiment Progress Details

Related Kernels (Level 1, Task 6 • 6_Matmul_with_large_K_dimension_)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 double_buffered_matmul_base 5.11 0.07 0.11
🥈 6_matmul_multi_stream_base 5.26 0.07 0.11
🥉 fewer_sync_matmul_edit_1_base 5.27 0.07 0.11
4 atomic_operations_matmul_edit_1 5.27 0.07 0.11
5 6_matmul_modular_refactored_base 5.30 0.06 0.11
6 modular_matmul_device_fn_edit_1 5.30 0.06 0.11
7 matmul_stream_ldg_base 5.31 0.06 0.11
8 6_matmul_modular_device_func_base 5.31 0.06 0.11
9 6_matmul_modular_device_base 5.32 0.06 0.11
10 6_matmul_no_divergence_base 5.32 0.06 0.11
11 6_matmul_ldg_base 5.33 0.06 0.11
12 optimized_streamed_tiled_matmul_base 5.33 0.06 0.11
12 6_matmul_even_workload_distribution_base 5.33 0.06 0.11
14 optimized_matmul_kernel_base 5.34 0.06 0.11
15 grid_stride_matmul_edit_1 5.34 0.06 0.11
16 6_matmul_stride_loops_base 5.34 0.06 0.11
17 6_matmul_ldg_128bit_aligned_base 5.35 0.06 0.11
18 optimized_matmul_kernel_base 5.35 0.06 0.11
19 unroll_loop_matmul_base 5.36 0.06 0.11
20 warp_divergence_optimized_matmul_base 5.37 0.06 0.11 
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>

#define TILE_WIDTH 16

// Device function to load a tile from matrix A into shared memory using __ldg()
template <typename scalar_t>
__device__ __forceinline__ void load_tile_A(const scalar_t* __restrict__ A,
                                              scalar_t tile_A[TILE_WIDTH][TILE_WIDTH],
                                              int row, int tile_idx, int K, int M) {
    int col = tile_idx * TILE_WIDTH + threadIdx.x;
    tile_A[threadIdx.y][threadIdx.x] = (row < M && col < K) ? __ldg(&A[row * K + col]) : static_cast<scalar_t>(0);
}

// Device function to load a tile from matrix B into shared memory using __ldg()
template <typename scalar_t>
__device__ __forceinline__ void load_tile_B(const scalar_t* __restrict__ B,
                                              scalar_t tile_B[TILE_WIDTH][TILE_WIDTH],
                                              int col, int tile_idx, int K, int N) {
    int row = tile_idx * TILE_WIDTH + threadIdx.y;
    tile_B[threadIdx.y][threadIdx.x] = (row < K && col < N) ? __ldg(&B[row * N + col]) : static_cast<scalar_t>(0);
}

// Device function to compute the partial dot product for the current tile
template <typename scalar_t>
__device__ __forceinline__ scalar_t compute_tile(const scalar_t tile_A[TILE_WIDTH][TILE_WIDTH],
                                                    const scalar_t tile_B[TILE_WIDTH][TILE_WIDTH]) {
    scalar_t partial = 0;
    #pragma unroll
    for (int i = 0; i < TILE_WIDTH; ++i) {
        partial += tile_A[threadIdx.y][i] * tile_B[i][threadIdx.x];
    }
    return partial;
}

// Modular CUDA kernel for matrix multiplication using shared memory tiling
// and modular device functions for loading and computing tiles
template <typename scalar_t>
__global__ void matmul_modular_refactored_kernel(const scalar_t* __restrict__ A,
                                                   const scalar_t* __restrict__ B,
                                                   scalar_t* __restrict__ C,
                                                   int M, int K, int N) {
    __shared__ scalar_t tile_A[TILE_WIDTH][TILE_WIDTH];
    __shared__ scalar_t tile_B[TILE_WIDTH][TILE_WIDTH];

    int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
    int col = blockIdx.x * TILE_WIDTH + threadIdx.x;
    scalar_t sum = 0;

    int num_tiles = (K + TILE_WIDTH - 1) / TILE_WIDTH;

    for (int t = 0; t < num_tiles; ++t) {
        load_tile_A<scalar_t>(A, tile_A, row, t, K, M);
        load_tile_B<scalar_t>(B, tile_B, col, t, K, N);
        __syncthreads();

        sum += compute_tile<scalar_t>(tile_A, tile_B);
        __syncthreads();
    }

    if (row < M && col < N) {
        C[row * N + col] = sum;
    }
}

// Host function to launch the CUDA kernel
torch::Tensor module_fn(torch::Tensor A, torch::Tensor B) {
    TORCH_CHECK(A.is_cuda(), "Input tensor A must be a CUDA tensor");
    TORCH_CHECK(B.is_cuda(), "Input tensor B must be a CUDA tensor");

    int64_t M = A.size(0);
    int64_t K = A.size(1);
    int64_t N = B.size(1);
    TORCH_CHECK(K == B.size(0), "Inner dimensions of A and B must match");

    auto C = torch::empty({M, N}, A.options());

    dim3 threads(TILE_WIDTH, TILE_WIDTH);
    dim3 blocks((N + TILE_WIDTH - 1) / TILE_WIDTH, (M + TILE_WIDTH - 1) / TILE_WIDTH);

    AT_DISPATCH_FLOATING_TYPES(A.scalar_type(), "matmul_modular_refactored_kernel", ([&] {
        matmul_modular_refactored_kernel<scalar_t><<<blocks, threads>>>(
            A.data_ptr<scalar_t>(),
            B.data_ptr<scalar_t>(),
            C.data_ptr<scalar_t>(),
            M, K, N
        );
    }));

    cudaDeviceSynchronize();
    return C;
}

// Pybind11 module binding
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &module_fn, "Matrix multiplication using modular device functions (CUDA)");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 0.830 inst/cycle 0.000 5
Executed Ipc Elapsed 0.820 inst/cycle 0.000 5
Issue Slots Busy 20.840 % 0.000 5
Issued Ipc Active 0.830 inst/cycle 0.000 5
SM Busy 20.840 % 0.000 5
Memory Throughput 47215204996.410 byte/second 1584802006113210.500 5
Mem Busy 42.566 % 0.001 5
Max Bandwidth 36.218 % 0.001 5
L1/TEX Hit Rate 0.318 % 0.001 5
L2 Hit Rate 83.060 % 0.007 5
Mem Pipes Busy 33.428 % 0.001 5
Warp Cycles Per Issued Instruction 18.530 cycle 0.000 5
Warp Cycles Per Executed Instruction 18.530 cycle 0.000 5
Avg. Active Threads Per Warp 32.000 0.000 5
Avg. Not Predicated Off Threads Per Warp 32.000 0.000 5
Max Active Clusters 0.000 cluster 0.000 5
Max Cluster Size 8.000 block 0.000 5
Overall GPU Occupancy 0.000 % 0.000 5
Cluster Occupancy 0.000 % 0.000 5
Block Limit SM 32.000 block 0.000 5
Block Limit Registers 8.000 block 0.000 5
Block Limit Shared Mem 21.000 block 0.000 5
Block Limit Warps 8.000 block 0.000 5
Theoretical Active Warps per SM 64.000 warp 0.000 5
Theoretical Occupancy 100.000 % 0.000 5
Achieved Occupancy 24.132 % 0.000 5
Achieved Active Warps Per SM 15.442 warp 0.000 5
Analysis Rules
Rule Description
WRN HighPipeUtilization All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (24.1%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
Operation / Metric Value Unit
aten::to
CPU Time 362175.13 μs
Device Time 27883.38 μs
Self CPU Time 48.95 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 362126.18 μs
Device Time 27883.38 μs
Self CPU Time 124.63 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::empty_strided
CPU Time 333717.57 μs
Device Time 0.00 μs
Self CPU Time 100.60 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaDeviceGetStreamPriorityRange
CPU Time 330615.02 μs
Device Time 0.00 μs
Self CPU Time 330615.02 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void matmul_modular_refactored_kernel<float>(float const*, float const*, float*, int, int, int)
CPU Time 0.00 μs
Device Time 8188320.31 μs
Self CPU Time 0.00 μs
Self Device Time 8188320.31 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaDeviceSynchronize
CPU Time 8290983.67 μs
Device Time 10457.75 μs
Self CPU Time 8290983.67 μs
Self Device Time 10457.75 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 21126.64 μs
Device Time 119857.54 μs
Self CPU Time 3542.12 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 17589.13 μs
Device Time 119857.54 μs
Self CPU Time 4722.64 μs
Self Device Time 119857.54 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 119857.54 μs
Self CPU Time 0.00 μs
Self Device Time 119857.54 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Completed 
45285 warnings generated when compiling for host.
Suppressed 45322 warnings (45275 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:11:47 bugprone-easily-swappable-parameters
11 | int row, int tile_idx, int K, int M) {
| ^~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:11:51: note: the first parameter in the range is 'row'
11 | int row, int tile_idx, int K, int M) {
| ^~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:11:60: note: the last parameter in the range is 'tile_idx'
11 | int row, int tile_idx, int K, int M) {
| ^~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:12:15: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
12 | int col = tile_idx * TILE_WIDTH + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:20:47: warning: 2 adjacent parameters of 'load_tile_B' of similar type ('int') are easily swapped by mistake [bugprone-easily-swappable-parameters]
20 | int col, int tile_idx, int K, int N) {
| ^~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:20:51: note: the first parameter in the range is 'col'
20 | int col, int tile_idx, int K, int N) {
| ^~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:20:60: note: the last parameter in the range is 'tile_idx'
20 | int col, int tile_idx, int K, int N) {
| ^~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:21:15: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
21 | int row = tile_idx * TILE_WIDTH + threadIdx.y;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:40:50: warning: 2 adjacent parameters of 'matmul_modular_refactored_kernel' of similar type ('const scalar_t *__restrict') are easily swapped by mistake [bugprone-easily-swappable-parameters]
40 | __global__ void matmul_modular_refactored_kernel(const scalar_t* __restrict__ A,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
41 | const scalar_t* __restrict__ B,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:40:79: note: the first parameter in the range is 'A'
40 | __global__ void matmul_modular_refactored_kernel(const scalar_t* __restrict__ A,
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:41:81: note: the last parameter in the range is 'B'
41 | const scalar_t* __restrict__ B,
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:47:15: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
47 | int row = blockIdx.y * TILE_WIDTH + threadIdx.y;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:48:15: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
48 | int col = blockIdx.x * TILE_WIDTH + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250202_optimize_b10_s4_e0_sweep/level_1/task_6/b9_s3_6_matmul_modular_refactored/base/base.cu:82:5: warning: inside a lambda, '__func__' expands to the name of the function call operator; consider capturing the name of the enclosing function explicitly [bugprone-lambda-function-name]
82 | AT_DISPATCH_FLOATING_TYPES(A.scalar_type(), "matmul_modular_refactored_kernel", ([&] {
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:237:34: note: expanded from macro 'AT_DISPATCH_FLOATING_TYPES'
237 | AT_DISPATCH_SWITCH(TYPE, NAME, AT_DISPATCH_CASE_FLOATING_TYPES(__VA_ARGS__))
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:233:3: note: expanded from macro 'AT_DISPATCH_CASE_FLOATING_TYPES'
233 | AT_DISPATCH_CASE(at::ScalarType::Double, __VA_ARGS__) \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:74:3: note: expanded from macro 'AT_DISPATCH_CASE'
74 | AT_PRIVATE_CASE_TYPE_USING_HINT(enum_type, scalar_t, __VA_ARGS__)
| ^
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:58:7: note: expanded from macro 'AT_PRIVATE_CHECK_SELECTIVE_BUILD'
58 | AT_ERROR( \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:711:32: note: expanded from macro 'AT_ERROR'
711 | C10_EXPAND_MSVC_WORKAROUND(TORCH_CHECK(false, ::c10::str(__VA_ARGS__))); \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:536:9: note: expanded from macro 'TORCH_CHECK'
536 | __func__, \
| ^