Kernel Details - fused_sigmoid_groupnorm

import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(
    x: torch.Tensor,
    conv_weight: torch.Tensor,
    conv_bias: torch.Tensor,
    bias: torch.Tensor,
    scale: torch.Tensor,
    group_norm_weight: torch.Tensor,
    group_norm_bias: torch.Tensor,
    num_groups: int,
) -> torch.Tensor:
    """
    Applies convolution, bias addition, scaling, sigmoid activation and group normalization.

    Args:
        x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width)
        conv_weight (torch.Tensor): Convolution weight tensor
        conv_bias (torch.Tensor): Convolution bias tensor
        bias (torch.Tensor): Bias tensor for addition
        scale (torch.Tensor): Scale tensor for multiplication
        group_norm_weight (torch.Tensor): Group norm weight tensor
        group_norm_bias (torch.Tensor): Group norm bias tensor
        num_groups (int): Number of groups for group normalization

    Returns:
        torch.Tensor: Output tensor after applying convolution, bias, scale, sigmoid and group norm
    """
    x = F.conv2d(x, conv_weight, bias=conv_bias)
    x = x + bias
    x = x * scale
    x = torch.sigmoid(x)
    x = F.group_norm(x, num_groups, group_norm_weight, group_norm_bias)
    return x


class Model(nn.Module):
    """
    Model that performs a convolution, adds a bias term, scales, applies sigmoid, and performs group normalization.
    """

    def __init__(
        self,
        in_channels,
        out_channels,
        kernel_size,
        num_groups,
        bias_shape,
        scale_shape,
    ):
        super(Model, self).__init__()
        conv = nn.Conv2d(in_channels, out_channels, kernel_size)
        self.conv_weight = conv.weight
        self.conv_bias = nn.Parameter(
            conv.bias + torch.ones_like(conv.bias) * 0.02
        )  # make sure its nonzero
        self.bias = nn.Parameter(torch.randn(bias_shape) * 0.02)
        self.scale = nn.Parameter(torch.randn(scale_shape) * 0.02)
        group_norm = nn.GroupNorm(num_groups, out_channels)
        self.group_norm_weight = group_norm.weight
        self.group_norm_bias = nn.Parameter(
            group_norm.bias + torch.ones_like(group_norm.bias) * 0.02
        )  # make sure its nonzero

    def forward(self, x, num_groups, fn=module_fn):
        return fn(
            x,
            self.conv_weight,
            self.conv_bias,
            self.bias,
            self.scale,
            self.group_norm_weight,
            self.group_norm_bias,
            num_groups,
        )


batch_size = 128
in_channels = 3
out_channels = 16
height, width = 32, 32
kernel_size = 3
num_groups = 8
bias_shape = (out_channels, 1, 1)
scale_shape = (out_channels, 1, 1)


def get_inputs():
    return [torch.randn(batch_size, in_channels, height, width), num_groups]


def get_init_inputs():
    return [in_channels, out_channels, kernel_size, num_groups, bias_shape, scale_shape]

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs a convolution, adds a bias term, scales, applies sigmoid, and performs group normalization.
    """
    def __init__(self, in_channels, out_channels, kernel_size, num_groups, bias_shape, scale_shape):
        super(Model, self).__init__()
        self.conv = nn.Conv2d(in_channels, out_channels, kernel_size)
        self.conv.bias = nn.Parameter(self.conv.bias + torch.ones_like(self.conv.bias) * 0.02)
        self.bias = nn.Parameter(torch.randn(bias_shape)*0.02) 
        self.scale = nn.Parameter(torch.randn(scale_shape)*0.02)
        self.group_norm = nn.GroupNorm(num_groups, out_channels)
        self.group_norm.bias = nn.Parameter(self.group_norm.bias + torch.ones_like(self.group_norm.bias) * 0.02)

    def forward(self, x):
        x = self.conv(x)
        x = x + self.bias
        x = x * self.scale
        x = torch.sigmoid(x)
        x = self.group_norm(x)
        return x

batch_size = 128
in_channels = 3
out_channels = 16
height, width = 32, 32
kernel_size = 3
num_groups = 8
bias_shape = (out_channels, 1, 1)
scale_shape = (out_channels, 1, 1)

def get_inputs():
    return [torch.randn(batch_size, in_channels, height, width)]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, num_groups, bias_shape, scale_shape]

Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name	21_Conv2d_Add_Scale_Sigmoid_GroupNorm
Level ID	2
Task ID	21
Kernel Name	fused_sigmoid_groupnorm_base
CUDA Speedup (Native)	1.596x
CUDA Speedup (Compile)	1.366x
CUDA Runtime	0.047 ms
PyTorch Runtime (Native)	0.075 ms
PyTorch Runtime (Compile)	0.064 ms
Correct	True
Max Diff (vs. Reference)	0.006000
Model	o3-mini-2025-01-31
Temperature	1.00

View Experiment Progress Details

Related Kernels (Level 2, Task 21 • 21_Conv2d_Add_Scale_Sigmoid_GroupNorm)

Rank	Kernel Name	Runtime (ms)	Speedup Native	Speedup Compile
🥇	shared_memory_coalesced_access_kernel_base	0.04	1.79	1.53
🥈	fused_elem_groupnorm_reduced_sync_base_base	0.04	1.74	1.49
🥈	fused_optimized_warp_base	0.04	1.74	1.49
🥈	optimized_memory_access_kernel_base	0.04	1.74	1.49
🥈	atomic_optimized_kernel_base_base	0.04	1.74	1.49
🥈	optimized_memory_access_kernel_base	0.04	1.74	1.49
🥈	optimized_fused_kernel_base	0.04	1.74	1.49
8	fused_warp_reduce_groupnorm_base	0.04	1.70	1.46
8	fused_warp_groupnorm_base	0.04	1.70	1.46
8	shared_memory_reuse_kernel_base	0.04	1.70	1.46
8	fused_lockfree_groupnorm_base_base	0.04	1.70	1.46
8	fused_stride_kernel_base	0.04	1.70	1.46
8	fused_elem_groupnorm_no_atomic_base	0.04	1.70	1.46
8	fused_elem_groupnorm_min_sync_base_base	0.04	1.70	1.46
8	unrolled_fused_kernel_base_base	0.04	1.70	1.46
16	optimized_modular_kernel_base	0.04	1.67	1.43
16	fused_strided_groupnorm_base_base	0.04	1.67	1.43
18	fused_sigmoid_groupnorm_base	0.05	1.63	1.40
19	fused_sigmoid_groupnorm_base	0.05	1.60	1.37
19	block_size_optimized_kernel_base_base	0.05	1.60	1.37

#include <torch/extension.h>
#include <ATen/ATen.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <math.h>

// Macro checks
#define CHECK_CUDA(x) TORCH_CHECK(x.is_cuda(), #x " must be a CUDA tensor.")
#define CHECK_CONTIGUOUS(x) TORCH_CHECK(x.is_contiguous(), #x " must be contiguous.")
#define CHECK_INPUT(x) CHECK_CUDA(x); CHECK_CONTIGUOUS(x)


// This kernel fuses the element-wise transformation (bias addition, scaling and sigmoid activation)
// with group normalization. Instead of writing the activation result to global memory and then reading it
// back for group normalization, the kernel computes local sums in registers, uses shared memory reduction
// to compute group mean and variance, and then re-computes the activation to produce the normalized output.
// Although the activation is computed twice, this eliminates extra global memory transactions, which is
// beneficial when the kernel is memory bound.

__global__ void fused_elemwise_groupnorm_kernel(
    const float* __restrict__ x,
    float* __restrict__ y,
    const float* __restrict__ bias,
    const float* __restrict__ scale,
    const float* __restrict__ gn_weight,
    const float* __restrict__ gn_bias,
    int N, int C, int H, int W,
    int num_groups,
    bool bias_broadcast,
    bool scale_broadcast,
    float eps) {

    // Each block is responsible for one group from one sample.
    int block_id = blockIdx.x; // block id runs from 0 to N*num_groups-1
    int sample_idx = block_id / num_groups;
    int group_idx = block_id % num_groups;

    int channels_per_group = C / num_groups;
    int group_size = channels_per_group * H * W;
    int sample_offset = sample_idx * C * H * W;
    int group_channel_offset = group_idx * channels_per_group;

    // Shared memory to perform reduction for sum and sum of squares
    extern __shared__ float shared_mem[];
    float* shared_sum = shared_mem;
    float* shared_sum_sq = &shared_mem[blockDim.x];

    int tid = threadIdx.x;
    int stride = blockDim.x;

    float local_sum = 0.0f;
    float local_sum_sq = 0.0f;

    // First pass: compute the element-wise activation and accumulate local sums
    // Activation: act = sigmoid((x + bias) * scale) = 1/(1+exp(-((x+bias)*scale)))
    for (int i = tid; i < group_size; i += stride) {
        int c_local = i / (H * W);
        int hw = i % (H * W);
        int c = group_channel_offset + c_local;
        int idx = sample_offset + c * H * W + hw;

        float x_val = __ldg(&x[idx]);
        float b_val = bias_broadcast ? __ldg(&bias[0]) : __ldg(&bias[c]);
        float s_val = scale_broadcast ? __ldg(&scale[0]) : __ldg(&scale[c]);

        float act = 1.0f / (1.0f + expf(-((x_val + b_val) * s_val)));
        local_sum += act;
        local_sum_sq += act * act;
    }

    // Write the results to shared memory
    shared_sum[tid] = local_sum;
    shared_sum_sq[tid] = local_sum_sq;
    __syncthreads();

    // Perform reduction in shared memory
    for (int s = blockDim.x / 2; s > 0; s >>= 1) {
        if (tid < s) {
            shared_sum[tid] += shared_sum[tid + s];
            shared_sum_sq[tid] += shared_sum_sq[tid + s];
        }
        __syncthreads();
    }

    // Calculate group mean and variance
    float mean = shared_sum[0] / group_size;
    float variance = shared_sum_sq[0] / group_size - mean * mean;
    float inv_std = rsqrtf(variance + eps);
    __syncthreads();

    // Second pass: re-compute activation and apply group normalization
    for (int i = tid; i < group_size; i += stride) {
        int c_local = i / (H * W);
        int hw = i % (H * W);
        int c = group_channel_offset + c_local;
        int idx = sample_offset + c * H * W + hw;

        float x_val = __ldg(&x[idx]);
        float b_val = bias_broadcast ? __ldg(&bias[0]) : __ldg(&bias[c]);
        float s_val = scale_broadcast ? __ldg(&scale[0]) : __ldg(&scale[c]);

        float act = 1.0f / (1.0f + expf(-((x_val + b_val) * s_val)));
        float normalized = (act - mean) * inv_std;

        float gamma = __ldg(&gn_weight[c]);
        float beta = __ldg(&gn_bias[c]);

        y[idx] = gamma * normalized + beta;
    }
}

// Launcher function for the fused kernel
void fused_elem_groupnorm_cuda(
    at::Tensor x,
    at::Tensor bias,
    at::Tensor scale,
    at::Tensor y,
    at::Tensor gn_weight,
    at::Tensor gn_bias,
    int64_t num_groups,
    bool bias_broadcast,
    bool scale_broadcast,
    float eps) {

    const int N = x.size(0);
    const int C = x.size(1);
    const int H = x.size(2);
    const int W = x.size(3);

    const int threads = 512;
    const int blocks = N * num_groups; // one block per group per sample
    const int shared_mem_size = 2 * threads * sizeof(float);

    fused_elemwise_groupnorm_kernel<<<blocks, threads, shared_mem_size>>>(
        x.data_ptr<float>(),
        y.data_ptr<float>(),
        bias.data_ptr<float>(),
        scale.data_ptr<float>(),
        gn_weight.data_ptr<float>(),
        gn_bias.data_ptr<float>(),
        N, C, H, W,
        num_groups,
        bias_broadcast,
        scale_broadcast,
        eps);

    cudaError_t err = cudaGetLastError();
    TORCH_CHECK(err == cudaSuccess, "CUDA kernel failed : ", cudaGetErrorString(err));
}

// Forward function exposed to Python. It performs convolution first, and then applies the fused kernel
// to perform the activation and group normalization in one pass.

at::Tensor module_fn_forward(
    at::Tensor x,
    at::Tensor conv_weight,
    at::Tensor conv_bias,
    at::Tensor bias,
    at::Tensor scale,
    at::Tensor gn_weight,
    at::Tensor gn_bias,
    int64_t num_groups) {

    CHECK_INPUT(x);
    CHECK_INPUT(conv_weight);
    if (conv_bias.defined()) CHECK_INPUT(conv_bias);
    CHECK_INPUT(bias);
    CHECK_INPUT(scale);
    CHECK_INPUT(gn_weight);
    CHECK_INPUT(gn_bias);

    // Perform convolution
    x = at::conv2d(x, conv_weight, conv_bias);

    // Allocate output tensor
    at::Tensor y = at::empty_like(x);

    fused_elem_groupnorm_cuda(
        x, bias, scale, y, gn_weight, gn_bias,
        num_groups,
        bias.numel() == 1,
        scale.numel() == 1,
        1e-5);

    return y;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &module_fn_forward, "Fused sigmoid and group normalization forward (CUDA)");
}

Performance Metrics

Metric	Value	Unit	Variance	Samples
Executed Ipc Active	2.616	inst/cycle	0.000	5
Executed Ipc Elapsed	2.216	inst/cycle	0.000	5
Issue Slots Busy	65.574	%	0.110	5
Issued Ipc Active	2.624	inst/cycle	0.000	5
SM Busy	65.574	%	0.110	5
Memory Throughput	395285099560.158	byte/second	4153031304901060096.000	5
Mem Busy	21.566	%	0.010	5
Max Bandwidth	20.618	%	0.010	5
L1/TEX Hit Rate	62.844	%	0.000	5
L2 Hit Rate	56.018	%	0.155	5
Mem Pipes Busy	29.770	%	0.020	5
Warp Cycles Per Issued Instruction	20.846	cycle	0.001	5
Warp Cycles Per Executed Instruction	20.900	cycle	0.001	5
Avg. Active Threads Per Warp	31.550		0.000	5
Avg. Not Predicated Off Threads Per Warp	27.500		0.000	5
Max Active Clusters	0.000	cluster	0.000	5
Max Cluster Size	8.000	block	0.000	5
Overall GPU Occupancy	0.000	%	0.000	5
Cluster Occupancy	0.000	%	0.000	5
Block Limit SM	32.000	block	0.000	5
Block Limit Registers	4.000	block	0.000	5
Block Limit Shared Mem	12.000	block	0.000	5
Block Limit Warps	4.000	block	0.000	5
Theoretical Active Warps per SM	64.000	warp	0.000	5
Theoretical Occupancy	100.000	%	0.000	5
Achieved Occupancy	85.846	%	0.015	5
Achieved Active Warps Per SM	54.940	warp	0.006	5

Analysis Rules

Rule	Description
INF HighPipeUtilization	ALU is the highest-utilized pipeline (46.3%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck.
WRN Occupancy	This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (85.8%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.

Rule

Description

INF HighPipeUtilization

ALU is the highest-utilized pipeline (46.3%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck.

WRN Occupancy

This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (85.8%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.

Operation / Metric	Value	Unit
aten::fill_
CPU Time	187189.84	μs
Device Time	1089240.98	μs
Self CPU Time	33350.65	μs
Self Device Time	1089240.98	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::zero_
CPU Time	213414.46	μs
Device Time	1089240.98	μs
Self CPU Time	26246.83	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::conv2d
CPU Time	1190236.20	μs
Device Time	387303.54	μs
Self CPU Time	25905.10	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::convolution
CPU Time	1164331.11	μs
Device Time	387303.54	μs
Self CPU Time	31090.63	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::_convolution
CPU Time	1133240.48	μs
Device Time	387303.54	μs
Self CPU Time	60689.72	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::cudnn_convolution
CPU Time	926103.02	μs
Device Time	276793.75	μs
Self CPU Time	228916.57	μs
Self Device Time	276793.75	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
cudaLaunchKernel
CPU Time	969458.77	μs
Device Time	28141.72	μs
Self CPU Time	969458.77	μs
Self Device Time	28141.72	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char, 1>)
CPU Time	0.00	μs
Device Time	1089240.98	μs
Self CPU Time	0.00	μs
Self Device Time	1089240.98	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B

Status: Completed

45310 warnings generated when compiling for host.
Suppressed 45328 warnings (45281 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.

/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_21/b4_s1_fused_sigmoid_groupnorm/base/base.cu:8:35 bugprone-macro-parentheses

8 | #define CHECK_CUDA(x) TORCH_CHECK(x.is_cuda(), #x " must be a CUDA tensor.")

| ^

| ()

/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_21/b4_s1_fused_sigmoid_groupnorm/base/base.cu:9:41: warning: macro argument should be enclosed in parentheses [bugprone-macro-parentheses]

9 | #define CHECK_CONTIGUOUS(x) TORCH_CHECK(x.is_contiguous(), #x " must be contiguous.")

| ^

| ()

/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_21/b4_s1_fused_sigmoid_groupnorm/base/base.cu:23:5: warning: 4 adjacent parameters of 'fused_elemwise_groupnorm_kernel' of similar type ('const float *__restrict') are easily swapped by mistake [bugprone-easily-swappable-parameters]

23 | const float* __restrict__ bias,

| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

24 | const float* __restrict__ scale,

| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

25 | const float* __restrict__ gn_weight,

| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

26 | const float* __restrict__ gn_bias,

| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_21/b4_s1_fused_sigmoid_groupnorm/base/base.cu:23:31: note: the first parameter in the range is 'bias'

23 | const float* __restrict__ bias,

| ^~~~

/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_21/b4_s1_fused_sigmoid_groupnorm/base/base.cu:26:31: note: the last parameter in the range is 'gn_bias'

26 | const float* __restrict__ gn_bias,

| ^~~~~~~

/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_21/b4_s1_fused_sigmoid_groupnorm/base/base.cu:27:5: warning: 2 adjacent parameters of 'fused_elemwise_groupnorm_kernel' of similar type ('int') are easily swapped by mistake [bugprone-easily-swappable-parameters]