47_Conv3d_Mish_Tanh
• manual_loop_unroll_fused_mish_tanh_base
import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
stride: int,
padding: int,
conv_weight: torch.Tensor,
conv_bias: torch.Tensor,
) -> torch.Tensor:
"""
Applies 3D convolution followed by Mish and Tanh activations.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W)
stride (int): Stride of the convolution
padding (int): Padding of the convolution
conv_weight (torch.Tensor): Convolution weight tensor of shape
(out_channels, in_channels, kernel_size, kernel_size, kernel_size)
conv_bias (torch.Tensor): Bias tensor for convolution of shape (out_channels)
Returns:
torch.Tensor: Output tensor after applying convolution, Mish and Tanh activations
"""
x = F.conv3d(x, conv_weight, bias=conv_bias, stride=stride, padding=padding)
x = F.mish(x)
x = torch.tanh(x)
return x
class Model(nn.Module):
"""
Model that performs a 3D convolution, applies Mish activation, and then applies Tanh activation.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride, padding):
super(Model, self).__init__()
conv = nn.Conv3d(
in_channels, out_channels, kernel_size, stride=stride, padding=padding
)
self.conv_weight = nn.Parameter(conv.weight)
self.conv_bias = nn.Parameter(
conv.bias
+ torch.randn(
conv.bias.shape, device=conv.bias.device, dtype=conv.bias.dtype
)
* 0.02
)
def forward(self, x, stride, padding, fn=module_fn):
return fn(x, stride, padding, self.conv_weight, self.conv_bias)
batch_size = 16
in_channels = 3
out_channels = 16
D, H, W = 16, 32, 32
kernel_size = 3
stride = 1
padding = 0
def get_inputs():
return [torch.randn(batch_size, in_channels, D, H, W), stride, padding]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Model that performs a 3D convolution, applies Mish activation, and then applies Tanh activation.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride=1, padding=0):
super(Model, self).__init__()
self.conv = nn.Conv3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)
self.conv.bias = nn.Parameter(self.conv.bias + torch.randn(self.conv.bias.shape, device=self.conv.bias.device, dtype=self.conv.bias.dtype) * 0.02)
def forward(self, x):
"""
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W).
Returns:
torch.Tensor: Output tensor of shape (batch_size, out_channels, D', H', W').
"""
x = self.conv(x)
x = torch.nn.functional.mish(x)
x = torch.tanh(x)
return x
batch_size = 16
in_channels = 3
out_channels = 16
D, H, W = 16, 32, 32
kernel_size = 3
def get_inputs():
return [torch.randn(batch_size, in_channels, D, H, W)]
def get_init_inputs():
return [in_channels, out_channels, kernel_size]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
#define BLOCK_SIZE 256
#define ELEMENTS_PER_THREAD 4
#define SHARED_MEM_SIZE (BLOCK_SIZE * ELEMENTS_PER_THREAD)
__device__ __forceinline__ float fused_mish_tanh_activation(float x) {
float softplus = logf(1.0f + expf(x));
float mish = x * tanhf(softplus);
return tanhf(mish);
}
__global__ void manual_loop_unroll_kernel(
float* __restrict__ output,
const float* __restrict__ input,
const int total_elements
) {
__shared__ float shared_data[SHARED_MEM_SIZE];
const int tid = threadIdx.x;
const int global_idx = blockIdx.x * SHARED_MEM_SIZE + tid;
// Load data into shared memory in coalesced manner
#pragma unroll
for (int i = 0; i < ELEMENTS_PER_THREAD; ++i) {
const int idx = global_idx + i * BLOCK_SIZE;
if (idx < total_elements) {
shared_data[tid + i * BLOCK_SIZE] = input[idx];
}
}
__syncthreads(); // Synchronize to ensure shared memory is fully populated
// Manually unroll the loop for processing the data
for (int i = 0; i < ELEMENTS_PER_THREAD; i += 4) {
const int idx_0 = global_idx + i * BLOCK_SIZE;
const int idx_1 = global_idx + (i + 1) * BLOCK_SIZE;
const int idx_2 = global_idx + (i + 2) * BLOCK_SIZE;
const int idx_3 = global_idx + (i + 3) * BLOCK_SIZE;
if (idx_0 < total_elements) {
shared_data[tid + i * BLOCK_SIZE] = fused_mish_tanh_activation(shared_data[tid + i * BLOCK_SIZE]);
output[idx_0] = shared_data[tid + i * BLOCK_SIZE];
}
if (idx_1 < total_elements) {
shared_data[tid + (i + 1) * BLOCK_SIZE] = fused_mish_tanh_activation(shared_data[tid + (i + 1) * BLOCK_SIZE]);
output[idx_1] = shared_data[tid + (i + 1) * BLOCK_SIZE];
}
if (idx_2 < total_elements) {
shared_data[tid + (i + 2) * BLOCK_SIZE] = fused_mish_tanh_activation(shared_data[tid + (i + 2) * BLOCK_SIZE]);
output[idx_2] = shared_data[tid + (i + 2) * BLOCK_SIZE];
}
if (idx_3 < total_elements) {
shared_data[tid + (i + 3) * BLOCK_SIZE] = fused_mish_tanh_activation(shared_data[tid + (i + 3) * BLOCK_SIZE]);
output[idx_3] = shared_data[tid + (i + 3) * BLOCK_SIZE];
}
}
}
torch::Tensor module_fn_forward(
torch::Tensor x,
int64_t stride,
int64_t padding,
torch::Tensor conv_weight,
torch::Tensor conv_bias
) {
TORCH_CHECK(x.is_cuda(), "Input tensor x must be a CUDA tensor");
TORCH_CHECK(conv_weight.is_cuda(), "Convolution weight must be a CUDA tensor");
TORCH_CHECK(conv_bias.is_cuda(), "Convolution bias must be a CUDA tensor");
auto x_conv = at::conv3d(
x,
conv_weight,
conv_bias,
{stride, stride, stride},
{padding, padding, padding}
);
auto output = torch::empty_like(x_conv);
const int total_elements = x_conv.numel();
const int num_blocks = (total_elements + SHARED_MEM_SIZE - 1) / SHARED_MEM_SIZE;
manual_loop_unroll_kernel<<<num_blocks, BLOCK_SIZE>>>(
output.data_ptr<float>(),
x_conv.data_ptr<float>(),
total_elements
);
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &module_fn_forward, "Manual loop unroll Mish-Tanh activation with shared memory (CUDA)");
}
Metric | Value | Unit | Variance | Samples |
---|---|---|---|---|
Executed Ipc Active | 2.936 | inst/cycle | 0.000 | 5 |
Executed Ipc Elapsed | 2.408 | inst/cycle | 0.000 | 5 |
Issue Slots Busy | 73.596 | % | 0.052 | 5 |
Issued Ipc Active | 2.944 | inst/cycle | 0.000 | 5 |
SM Busy | 73.596 | % | 0.052 | 5 |
Memory Throughput | 1015409327374.978 | byte/second | 28498234590931451904.000 | 5 |
Mem Busy | 26.098 | % | 0.015 | 5 |
Max Bandwidth | 30.388 | % | 0.026 | 5 |
L1/TEX Hit Rate | 0.000 | % | 0.000 | 5 |
L2 Hit Rate | 50.846 | % | 0.144 | 5 |
Mem Pipes Busy | 20.138 | % | 0.010 | 5 |
Warp Cycles Per Issued Instruction | 18.286 | cycle | 0.001 | 5 |
Warp Cycles Per Executed Instruction | 18.318 | cycle | 0.001 | 5 |
Avg. Active Threads Per Warp | 22.160 | 0.000 | 5 | |
Avg. Not Predicated Off Threads Per Warp | 21.270 | 0.000 | 5 | |
Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
Max Cluster Size | 8.000 | block | 0.000 | 5 |
Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
Cluster Occupancy | 0.000 | % | 0.000 | 5 |
Block Limit SM | 32.000 | block | 0.000 | 5 |
Block Limit Registers | 10.000 | block | 0.000 | 5 |
Block Limit Shared Mem | 20.000 | block | 0.000 | 5 |
Block Limit Warps | 8.000 | block | 0.000 | 5 |
Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
Achieved Occupancy | 84.590 | % | 0.007 | 5 |
Achieved Active Warps Per SM | 54.138 | warp | 0.003 | 5 |
Rule | Description |
---|---|
INF HighPipeUtilization | ALU is the highest-utilized pipeline (28.5%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck. |
WRN ThreadDivergence | Instructions are executed in warps, which are groups of 32 threads. Optimal instruction throughput is achieved if all 32 threads of a warp execute the same instruction. The chosen launch configuration, early thread completion, and divergent flow control can significantly lower the number of active threads in a warp per cycle. This kernel achieves an average of 22.2 threads being active per cycle. This is further reduced to 21.3 threads per warp due to predication. The compiler may use predication to avoid an actual branch. Instead, all instructions are scheduled, but a per-thread condition code or predicate controls which threads execute the instructions. Try to avoid different execution paths within a warp when possible. In addition, ensure your kernel makes use of Independent Thread Scheduling, which allows a warp to reconverge after a data-dependent conditional block by explicitly calling __syncwarp(). |
WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (84.5%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
Operation / Metric | Value | Unit |
---|---|---|
aten::conv3d | ||
CPU Time | 1198762.56 | μs |
Device Time | 1228200.73 | μs |
Self CPU Time | 23609.60 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::convolution | ||
CPU Time | 1175152.96 | μs |
Device Time | 1228200.73 | μs |
Self CPU Time | 30455.33 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::_convolution | ||
CPU Time | 1144697.64 | μs |
Device Time | 1228200.73 | μs |
Self CPU Time | 57904.90 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::cudnn_convolution | ||
CPU Time | 958929.15 | μs |
Device Time | 1071155.02 | μs |
Self CPU Time | 239079.33 | μs |
Self Device Time | 1071155.02 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
sm80_xmma_fprop_implicit_gemm_indexed_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize32x32x8_stage3_warpsize1x2x1_g1_ffma_aligna4_alignc4_execute_kernel__5x_cudnn | ||
CPU Time | 0.00 | μs |
Device Time | 1071152.11 | μs |
Self CPU Time | 0.00 | μs |
Self Device Time | 1071152.11 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
cudaLaunchKernel | ||
CPU Time | 1015679.38 | μs |
Device Time | 42959.92 | μs |
Self CPU Time | 1015679.38 | μs |
Self Device Time | 42959.92 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
45283 warnings generated when compiling for host. Suppressed 45325 warnings (45278 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.