import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
stride: int,
padding: int,
conv_weight: torch.Tensor,
conv_bias: torch.Tensor,
) -> torch.Tensor:
"""
Applies 3D convolution followed by Mish and Tanh activations.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W)
stride (int): Stride of the convolution
padding (int): Padding of the convolution
conv_weight (torch.Tensor): Convolution weight tensor of shape
(out_channels, in_channels, kernel_size, kernel_size, kernel_size)
conv_bias (torch.Tensor): Bias tensor for convolution of shape (out_channels)
Returns:
torch.Tensor: Output tensor after applying convolution, Mish and Tanh activations
"""
x = F.conv3d(x, conv_weight, bias=conv_bias, stride=stride, padding=padding)
x = F.mish(x)
x = torch.tanh(x)
return x
class Model(nn.Module):
"""
Model that performs a 3D convolution, applies Mish activation, and then applies Tanh activation.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride, padding):
super(Model, self).__init__()
conv = nn.Conv3d(
in_channels, out_channels, kernel_size, stride=stride, padding=padding
)
self.conv_weight = nn.Parameter(conv.weight)
self.conv_bias = nn.Parameter(
conv.bias
+ torch.randn(
conv.bias.shape, device=conv.bias.device, dtype=conv.bias.dtype
)
* 0.02
)
def forward(self, x, stride, padding, fn=module_fn):
return fn(x, stride, padding, self.conv_weight, self.conv_bias)
batch_size = 16
in_channels = 3
out_channels = 16
D, H, W = 16, 32, 32
kernel_size = 3
stride = 1
padding = 0
def get_inputs():
return [torch.randn(batch_size, in_channels, D, H, W), stride, padding]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, stride, padding]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Model that performs a 3D convolution, applies Mish activation, and then applies Tanh activation.
"""
def __init__(self, in_channels, out_channels, kernel_size, stride=1, padding=0):
super(Model, self).__init__()
self.conv = nn.Conv3d(in_channels, out_channels, kernel_size, stride=stride, padding=padding)
self.conv.bias = nn.Parameter(self.conv.bias + torch.randn(self.conv.bias.shape, device=self.conv.bias.device, dtype=self.conv.bias.dtype) * 0.02)
def forward(self, x):
"""
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W).
Returns:
torch.Tensor: Output tensor of shape (batch_size, out_channels, D', H', W').
"""
x = self.conv(x)
x = torch.nn.functional.mish(x)
x = torch.tanh(x)
return x
batch_size = 16
in_channels = 3
out_channels = 16
D, H, W = 16, 32, 32
kernel_size = 3
def get_inputs():
return [torch.randn(batch_size, in_channels, D, H, W)]
def get_init_inputs():
return [in_channels, out_channels, kernel_size]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
// Device function performing fused activation: Mish followed by Tanh
// Mish(x) = x * tanhf(softplus(x)) with softplus(x) = log(1 + exp(x))
// Final output = tanhf(mish(x))
__device__ __forceinline__ float fused_mish_tanh_activation(float x) {
float softplus = logf(1.0f + expf(x));
float mish = x * tanhf(softplus);
return tanhf(mish);
}
// CUDA kernel using grid-stride loops with vectorized processing (float4) for improved workload distribution
// and handling of larger workloads than the available threads with correct boundary checks.
__global__ void stride_loop_mish_tanh_kernel(
float* __restrict__ output,
const float* __restrict__ input,
const int total_elements,
const int total_vec4
) {
// Calculate global thread index and overall stride
int global_tid = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Process main data in chunks of 4 elements at a time using vectorized float4 operations
for (int i = global_tid; i < total_vec4; i += stride) {
// Load 4 elements at once
float4 in_val = reinterpret_cast<const float4*>(input)[i];
float4 out_val;
float* in_ptr = reinterpret_cast<float*>(&in_val);
float* out_ptr = reinterpret_cast<float*>(&out_val);
#pragma unroll
for (int j = 0; j < 4; j++) {
out_ptr[j] = fused_mish_tanh_activation(in_ptr[j]);
}
reinterpret_cast<float4*>(output)[i] = out_val;
}
// Process any remaining elements individually if total_elements is not a multiple of 4
int vectorized_total = total_vec4 * 4;
for (int i = global_tid + vectorized_total; i < total_elements; i += stride) {
output[i] = fused_mish_tanh_activation(input[i]);
}
}
// Module forward function: applies 3D convolution followed by fused Mish-Tanh activation
torch::Tensor module_fn_forward(
torch::Tensor x,
int64_t stride,
int64_t padding,
torch::Tensor conv_weight,
torch::Tensor conv_bias
) {
TORCH_CHECK(x.is_cuda(), "Input tensor x must be a CUDA tensor");
TORCH_CHECK(conv_weight.is_cuda(), "Convolution weight must be a CUDA tensor");
TORCH_CHECK(conv_bias.is_cuda(), "Convolution bias must be a CUDA tensor");
// Perform 3D convolution using PyTorch's optimized conv3d
auto x_conv = at::conv3d(
x,
conv_weight,
conv_bias,
{stride, stride, stride},
{padding, padding, padding}
);
// Prepare output tensor and compute number of elements
auto output = torch::empty_like(x_conv);
int total_elements = x_conv.numel();
int total_vec4 = total_elements / 4; // number of complete groups of 4 elements
// Configure CUDA kernel launch using grid-stride loop to cover all data
const int block_size = 256;
int num_blocks = (total_vec4 + block_size - 1) / block_size;
// Ensure we cover the tail elements as well
if(num_blocks < 1) num_blocks = 1;
stride_loop_mish_tanh_kernel<<<num_blocks, block_size>>>(
output.data_ptr<float>(),
x_conv.data_ptr<float>(),
total_elements,
total_vec4
);
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &module_fn_forward, "Fused conv3d with grid-stride loop Mish-Tanh activation (CUDA)");
}
Metric | Value | Unit | Variance | Samples |
---|---|---|---|---|
Executed Ipc Active | 2.820 | inst/cycle | 0.001 | 5 |
Executed Ipc Elapsed | 2.296 | inst/cycle | 0.000 | 5 |
Issue Slots Busy | 71.150 | % | 0.429 | 5 |
Issued Ipc Active | 2.846 | inst/cycle | 0.001 | 5 |
SM Busy | 71.150 | % | 0.429 | 5 |
Memory Throughput | 1072530513723.520 | byte/second | 37237995222695395328.000 | 5 |
Mem Busy | 27.556 | % | 0.042 | 5 |
Max Bandwidth | 32.078 | % | 0.045 | 5 |
L1/TEX Hit Rate | 0.000 | % | 0.000 | 5 |
L2 Hit Rate | 50.646 | % | 0.035 | 5 |
Mem Pipes Busy | 12.584 | % | 0.006 | 5 |
Warp Cycles Per Issued Instruction | 18.398 | cycle | 0.008 | 5 |
Warp Cycles Per Executed Instruction | 18.568 | cycle | 0.008 | 5 |
Avg. Active Threads Per Warp | 21.180 | 0.000 | 5 | |
Avg. Not Predicated Off Threads Per Warp | 20.500 | 0.000 | 5 | |
Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
Max Cluster Size | 8.000 | block | 0.000 | 5 |
Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
Cluster Occupancy | 0.000 | % | 0.000 | 5 |
Block Limit SM | 32.000 | block | 0.000 | 5 |
Block Limit Registers | 10.000 | block | 0.000 | 5 |
Block Limit Shared Mem | 32.000 | block | 0.000 | 5 |
Block Limit Warps | 8.000 | block | 0.000 | 5 |
Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
Achieved Occupancy | 82.146 | % | 0.240 | 5 |
Achieved Active Warps Per SM | 52.572 | warp | 0.097 | 5 |
Rule | Description |
---|---|
INF HighPipeUtilization | FMA is the highest-utilized pipeline (30.1%) based on active cycles, taking into account the rates of its different instructions. It executes 32-bit floating point (FADD, FMUL, FMAD, ...) and integer (IMUL, IMAD) operations. It is well-utilized, but should not be a bottleneck. |
WRN ThreadDivergence | Instructions are executed in warps, which are groups of 32 threads. Optimal instruction throughput is achieved if all 32 threads of a warp execute the same instruction. The chosen launch configuration, early thread completion, and divergent flow control can significantly lower the number of active threads in a warp per cycle. This kernel achieves an average of 21.2 threads being active per cycle. This is further reduced to 20.5 threads per warp due to predication. The compiler may use predication to avoid an actual branch. Instead, all instructions are scheduled, but a per-thread condition code or predicate controls which threads execute the instructions. Try to avoid different execution paths within a warp when possible. In addition, ensure your kernel makes use of Independent Thread Scheduling, which allows a warp to reconverge after a data-dependent conditional block by explicitly calling __syncwarp(). |
WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (82.4%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
Operation / Metric | Value | Unit |
---|---|---|
aten::conv3d | ||
CPU Time | 1186915.27 | μs |
Device Time | 1172492.94 | μs |
Self CPU Time | 22338.06 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::convolution | ||
CPU Time | 1164577.21 | μs |
Device Time | 1172492.94 | μs |
Self CPU Time | 29125.95 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::_convolution | ||
CPU Time | 1135451.25 | μs |
Device Time | 1172492.94 | μs |
Self CPU Time | 55904.46 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::cudnn_convolution | ||
CPU Time | 954894.00 | μs |
Device Time | 1021231.17 | μs |
Self CPU Time | 249723.23 | μs |
Self Device Time | 1021231.17 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
sm80_xmma_fprop_implicit_gemm_indexed_f32f32_f32f32_f32_nchwkcrs_nchw_tilesize32x32x8_stage3_warpsize1x2x1_g1_ffma_aligna4_alignc4_execute_kernel__5x_cudnn | ||
CPU Time | 0.00 | μs |
Device Time | 1021228.42 | μs |
Self CPU Time | 0.00 | μs |
Self Device Time | 1021228.42 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
cudaLaunchKernel | ||
CPU Time | 957266.16 | μs |
Device Time | 40984.32 | μs |
Self CPU Time | 957266.16 | μs |
Self Device Time | 40984.32 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
45284 warnings generated when compiling for host. Suppressed 45325 warnings (45278 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.