Kernel Details - fused_rg_no_divergence

import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(
    x: torch.Tensor,
    conv_transpose: torch.Tensor,
    group_norm_weight: torch.Tensor,
    group_norm_bias: torch.Tensor,
    groups: int,
    eps: float,
) -> torch.Tensor:
    """
    Applies a transposed 3D convolution, ReLU, and group normalization.

    Args:
        x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W)
        conv_transpose (torch.Tensor): Transposed convolution weight tensor
        group_norm_weight (torch.Tensor): Weight tensor for group normalization
        group_norm_bias (torch.Tensor): Bias tensor for group normalization
        groups (int): Number of groups for group normalization
        eps (float): Epsilon for group normalization
    Returns:
        torch.Tensor: Output tensor of shape (batch_size, out_channels, D, H, W)
    """
    x = F.conv_transpose3d(x, conv_transpose, bias=None)
    x = F.relu(x)
    x = F.group_norm(x, groups, group_norm_weight, group_norm_bias, eps)
    return x


class Model(nn.Module):
    """
    Model that performs a transposed 3D convolution, applies ReLU, and then applies group normalization.
    """

    def __init__(self, in_channels, out_channels, kernel_size, groups, bias):
        super(Model, self).__init__()
        conv = nn.ConvTranspose3d(in_channels, out_channels, kernel_size)
        self.conv_transpose_parameter = conv.weight

        # set torch seed to 0
        torch.manual_seed(0)
        gn = nn.GroupNorm(num_groups=groups, num_channels=out_channels, eps=eps)
        self.group_norm_weight = nn.Parameter(
            gn.weight + torch.randn_like(gn.weight) * 0.02
        )
        self.group_norm_bias = nn.Parameter(gn.bias + torch.randn_like(gn.bias) * 0.02)

    def forward(self, x, fn=module_fn):
        return fn(
            x,
            self.conv_transpose_parameter,
            self.group_norm_weight,
            self.group_norm_bias,
            groups,
            eps,
        )


batch_size = 16
in_channels = 64
out_channels = 128
D, H, W = 8, 16, 16
kernel_size = 3
groups = 8
bias = False
eps = 1e-5


def get_inputs():
    return [torch.randn(batch_size, in_channels, D, H, W)]


def get_init_inputs():
    return [in_channels, out_channels, kernel_size, groups, bias]

import torch
import torch.nn as nn


class Model(nn.Module):
    """
    Model that performs a transposed 3D convolution, applies ReLU, and then applies group normalization.
    """

    def __init__(
        self, in_channels, out_channels, kernel_size, groups, bias=False, eps=1e-5
    ):
        super(Model, self).__init__()
        self.conv_transpose = nn.ConvTranspose3d(
            in_channels, out_channels, kernel_size, bias=bias
        )
        self.relu = nn.ReLU()
        # set torch seed to 0
        torch.manual_seed(0)
        self.group_norm = nn.GroupNorm(
            num_groups=groups, num_channels=out_channels, eps=eps
        )
        self.group_norm.weight = nn.Parameter(
            self.group_norm.weight + torch.randn_like(self.group_norm.weight) * 0.02
        )
        self.group_norm.bias = nn.Parameter(
            self.group_norm.bias + torch.randn_like(self.group_norm.bias) * 0.02
        )

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_channels, D, H, W).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_channels, D, H, W).
        """
        x = self.conv_transpose(x)
        x = self.relu(x)
        x = self.group_norm(x)
        return x


batch_size = 16
in_channels = 64
out_channels = 128
D, H, W = 8, 16, 16
kernel_size = 3
groups = 8
bias = False


def get_inputs():
    return [torch.randn(batch_size, in_channels, D, H, W)]


def get_init_inputs():
    return [in_channels, out_channels, kernel_size, groups, bias]

Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name	61_ConvTranspose3d_ReLU_GroupNorm
Level ID	2
Task ID	61
Kernel Name	fused_rg_no_divergence_base
CUDA Speedup (Native)	1.160x
CUDA Speedup (Compile)	0.989x
CUDA Runtime	0.213 ms
PyTorch Runtime (Native)	0.247 ms
PyTorch Runtime (Compile)	0.211 ms
Correct	True
Max Diff (vs. Reference)	0.000000
Model	o3-mini-2025-01-31
Temperature	1.00

View Experiment Progress Details

Related Kernels (Level 2, Task 61 • 61_ConvTranspose3d_ReLU_GroupNorm)

Rank	Kernel Name	Runtime (ms)	Speedup Native	Speedup Compile
🥇	fused_rg_atomic_opt_base_base	0.18	1.34	1.14
🥈	fused_rg_warp_opt_base_base	0.18	1.34	1.14
🥉	optimized_fused_relu_groupnorm_base	0.19	1.31	1.11
4	fused_rg_atomic_min_base_base	0.19	1.29	1.10
5	fused_rg_dynamic_bs_opt_base	0.20	1.27	1.08
6	fused_rg_aligned_base_base	0.20	1.22	1.04
7	fused_rg_even_work_base	0.21	1.20	1.02
8	fused_rg_coalesced_base	0.21	1.19	1.02
9	fused_rg_const_base_base	0.21	1.19	1.01
10	fused_rg_const_base_base	0.21	1.16	0.99
10	fused_rg_no_divergence_base	0.21	1.16	0.99
12	fused_rg_modular_base	0.21	1.15	0.98
13	61_ConvTranspose3d_ReLU_GroupNorm_modular_base	0.23	1.09	0.93
14	61_ConvTranspose3d_ReLU_GroupNorm_modular_edit_1	0.23	1.09	0.93
15	61_ConvTranspose3d_ReLU_GroupNorm_grid_stride_base	0.23	1.08	0.92
15	61_ConvTranspose3d_ReLU_GroupNorm_aligned_memory_edit_1	0.23	1.08	0.92
15	61_ConvTranspose3d_ReLU_GroupNorm_modular_base	0.23	1.08	0.92
15	61_ConvTranspose3d_ReLU_GroupNorm_aligned_memory_base	0.23	1.08	0.92
19	61_convtranspose3d_relu_groupnorm_unroll_edit_1	0.23	1.07	0.92
19	61_ConvTranspose3d_ReLU_GroupNorm_grid_stride_edit_1	0.23	1.07	0.92

#include <pybind11/pybind11.h>
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>

#define BLOCK_SIZE 256
#define WARP_SIZE 32

// This kernel fuses ReLU and GroupNorm with minimized warp divergence.
// It refactors conditional logic into uniform loops and uses vectorized memory accesses for the main body.

__global__ void fused_relu_groupnorm_no_div_kernel(
    float* __restrict__ data,            // tensor of shape [N, C, D, H, W]
    const float* __restrict__ gamma,       // GroupNorm weight, shape: [C]
    const float* __restrict__ beta,        // GroupNorm bias, shape: [C]
    int N, int C, int D, int H, int W,
    int G, float eps)                      // groups and epsilon
{
    // Compute tensor dimensions
    int spatial_size = D * H * W;
    int channels_per_group = C / G;

    // Identify current sample and group
    int n = blockIdx.x;  // sample index
    int g = blockIdx.y;  // group index
    int c_start = g * channels_per_group;

    // Pointer to the current group's data
    int group_offset = n * (C * spatial_size) + c_start * spatial_size;
    float* group_data = data + group_offset;
    int group_elems = channels_per_group * spatial_size;

    // Allocate shared memory:
    // - First: load gamma and beta for this group (each array of size channels_per_group)
    // - Next: two arrays for warp reduction (WARP_SIZE each for sum and sumsq)
    extern __shared__ float s_mem[];
    float* sh_gamma = s_mem;                         // size: channels_per_group floats
    float* sh_beta  = sh_gamma + channels_per_group;   // size: channels_per_group floats
    float* s_sum    = sh_beta + channels_per_group;    // size: WARP_SIZE floats
    float* s_sumsq  = s_sum + WARP_SIZE;               // size: WARP_SIZE floats

    // Uniformly load GroupNorm parameters into shared memory
    for (int i = threadIdx.x; i < channels_per_group; i += blockDim.x) {
        sh_gamma[i] = gamma[g * channels_per_group + i];
        sh_beta[i]  = beta[g * channels_per_group + i];
    }
    __syncthreads();

    // First pass: Apply ReLU and accumulate sum and sum-of-squares.
    float local_sum = 0.f;
    float local_sumsq = 0.f;

    // Process as many elements as possible with vectorized loads (float4) for coalesced access
    int num_vec = group_elems >> 2;  // equivalent to group_elems / 4
    float4* group_data4 = reinterpret_cast<float4*>(group_data);

    for (int i = threadIdx.x; i < num_vec; i += blockDim.x) {
        float4 v = group_data4[i];
        // Apply ReLU in a branchless manner
        v.x = fmaxf(v.x, 0.f);
        v.y = fmaxf(v.y, 0.f);
        v.z = fmaxf(v.z, 0.f);
        v.w = fmaxf(v.w, 0.f);
        group_data4[i] = v;
        
        float sum_val = v.x + v.y + v.z + v.w;
        float sumsq_val = v.x*v.x + v.y*v.y + v.z*v.z + v.w*v.w;
        local_sum += sum_val;
        local_sumsq += sumsq_val;
    }

    // Process remaining elements (if group_elems is not divisible by 4)
    int start = num_vec << 2; // start index for remainder
    int rem = group_elems - start;  // remainder count (<4)
    int num_rem_iters = (rem + blockDim.x - 1) / blockDim.x;
    for (int i = 0; i < num_rem_iters; i++) {
        int idx = start + i * blockDim.x + threadIdx.x;
        if (idx < group_elems) {
            float val = group_data[idx];
            float r = fmaxf(val, 0.f);
            group_data[idx] = r;
            local_sum += r;
            local_sumsq += r * r;
        }
    }

    // Warp-level reduction using shuffle intrinsics for uniform control flow
    unsigned int mask = 0xffffffff;
    int lane = threadIdx.x & (WARP_SIZE - 1);
    for (int offset = WARP_SIZE / 2; offset > 0; offset /= 2) {
        local_sum  += __shfl_down_sync(mask, local_sum, offset);
        local_sumsq += __shfl_down_sync(mask, local_sumsq, offset);
    }

    // Write warp-level results to shared memory
    int warp_id = threadIdx.x / WARP_SIZE;
    if (lane == 0) {
        s_sum[warp_id] = local_sum;
        s_sumsq[warp_id] = local_sumsq;
    }
    __syncthreads();

    // Final block-level reduction by thread 0
    if (threadIdx.x == 0) {
        float group_sum = 0.f;
        float group_sumsq = 0.f;
        int num_warps = (blockDim.x + WARP_SIZE - 1) / WARP_SIZE;
        for (int i = 0; i < num_warps; i++) {
            group_sum  += s_sum[i];
            group_sumsq += s_sumsq[i];
        }
        float mean = group_sum / group_elems;
        float var = group_sumsq / group_elems - mean * mean;
        float inv_std = rsqrtf(var + eps);
        s_sum[0] = mean;       // broadcast mean
        s_sumsq[0] = inv_std;  // broadcast inverse std
    }
    __syncthreads();

    float mean = s_sum[0];
    float inv_std = s_sumsq[0];

    // Second pass: Normalize the data using loaded gamma and beta from shared memory
    for (int i = threadIdx.x; i < group_elems; i += blockDim.x) {
        int channel = i / spatial_size;  // Determine channel index within the group
        float g_val = sh_gamma[channel];
        float b_val = sh_beta[channel];
        float norm_val = (group_data[i] - mean) * inv_std;
        group_data[i] = norm_val * g_val + b_val;
    }
}

// Forward function: First performs 3D transposed convolution, then applies the fused kernel

torch::Tensor forward(
    torch::Tensor x,
    torch::Tensor conv_transpose,
    torch::Tensor group_norm_weight,
    torch::Tensor group_norm_bias,
    int64_t groups,
    double eps) {

    // Perform 3D transposed convolution using the ATen operator
    auto y = at::conv_transpose3d(
        x,
        conv_transpose,
        /*bias=*/c10::nullopt,
        /*stride=*/{1, 1, 1},
        /*padding=*/{0, 0, 0},
        /*output_padding=*/{0, 0, 0},
        /*groups=*/1,
        /*dilation=*/{1, 1, 1}
    );

    int N = y.size(0);
    int C = y.size(1);
    int D = y.size(2);
    int H = y.size(3);
    int W = y.size(4);
    int G = groups;
    int channels_per_group = C / G;
    int spatial_size = D * H * W;

    // Calculate shared memory size in bytes:
    // - Two arrays for gamma and beta: 2 * channels_per_group floats
    // - Two warp reduction arrays: 2 * WARP_SIZE floats
    size_t shared_mem_size = (channels_per_group * 2 + 2 * WARP_SIZE) * sizeof(float);

    dim3 grid(N, G);
    dim3 block(BLOCK_SIZE);

    fused_relu_groupnorm_no_div_kernel<<<grid, block, shared_mem_size>>>(
         y.data_ptr<float>(),
         group_norm_weight.data_ptr<float>(),
         group_norm_bias.data_ptr<float>(),
         N, C, D, H, W,
         G, static_cast<float>(eps)
    );

    cudaDeviceSynchronize();
    return y;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &forward, "Fused ConvTranspose3D + ReLU + GroupNorm with minimized warp divergence (CUDA)");
}

Performance Metrics

Metric	Value	Unit	Variance	Samples
Executed Ipc Active	0.758	inst/cycle	0.000	5
Executed Ipc Elapsed	0.666	inst/cycle	0.000	5
Issue Slots Busy	18.966	%	0.005	5
Issued Ipc Active	0.758	inst/cycle	0.000	5
SM Busy	19.838	%	0.005	5
Memory Throughput	861432738929.230	byte/second	32785721240598818816.000	5
Mem Busy	20.188	%	0.023	5
Max Bandwidth	27.730	%	0.046	5
L1/TEX Hit Rate	74.950	%	0.000	5
L2 Hit Rate	67.366	%	0.001	5
Mem Pipes Busy	9.094	%	0.005	5
Warp Cycles Per Issued Instruction	10.520	cycle	0.000	5
Warp Cycles Per Executed Instruction	10.528	cycle	0.000	5
Avg. Active Threads Per Warp	31.960		0.000	5
Avg. Not Predicated Off Threads Per Warp	28.050		0.000	5
Max Active Clusters	0.000	cluster	0.000	5
Max Cluster Size	8.000	block	0.000	5
Overall GPU Occupancy	0.000	%	0.000	5
Cluster Occupancy	0.000	%	0.000	5
Block Limit SM	32.000	block	0.000	5
Block Limit Registers	8.000	block	0.000	5
Block Limit Shared Mem	23.000	block	0.000	5
Block Limit Warps	8.000	block	0.000	5
Theoretical Active Warps per SM	64.000	warp	0.000	5
Theoretical Occupancy	100.000	%	0.000	5
Achieved Occupancy	12.490	%	0.000	5
Achieved Active Warps Per SM	7.990	warp	0.000	5

Analysis Rules

Rule	Description
WRN HighPipeUtilization	All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details.
INF CPIStall	Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN Occupancy	This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (12.5%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.

Operation / Metric	Value	Unit
aten::to
CPU Time	387169.32	μs
Device Time	792.92	μs
Self CPU Time	56.12	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::conv_transpose3d
CPU Time	419241.27	μs
Device Time	1077724.20	μs
Self CPU Time	10567.85	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::convolution
CPU Time	408673.42	μs
Device Time	1077724.20	μs
Self CPU Time	16260.12	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::_convolution
CPU Time	392413.30	μs
Device Time	1077724.20	μs
Self CPU Time	17611.94	μs
Self Device Time	0.00	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
aten::cudnn_convolution_transpose
CPU Time	374801.36	μs
Device Time	1077724.20	μs
Self CPU Time	189469.21	μs
Self Device Time	1077724.20	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
sm90_xmma_dgrad_implicit_gemm_f32f32_tf32f32_f32_nhwckrsc_nhwc_tilesize256x64x32_warpgroupsize1x1x1_g1_execute_segment_k_off_kernel__5x_cudnn
CPU Time	0.00	μs
Device Time	833369.88	μs
Self CPU Time	0.00	μs
Self Device Time	833369.88	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B
cudaDeviceSynchronize
CPU Time	1647084.35	μs
Device Time	112605.15	μs
Self CPU Time	1647084.35	μs
Self Device Time	112605.15	μs
CPU Memory Usage	0	B
Device Memory Usage	0	B
Self CPU Memory Usage	0	B
Self Device Memory Usage	0	B

Status: Completed

45307 warnings generated when compiling for host.
Suppressed 45323 warnings (45276 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.

/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_2/task_61/b7_s3_fused_rg_no_divergence/base/base.cu:14:5 bugprone-easily-swappable-parameters

14 | const float* __restrict__ gamma, // GroupNorm weight, shape: [C]

| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

15 | const float* __restrict__ beta, // GroupNorm bias, shape: [C]

| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_2/task_61/b7_s3_fused_rg_no_divergence/base/base.cu:14:31: note: the first parameter in the range is 'gamma'

14 | const float* __restrict__ gamma, // GroupNorm weight, shape: [C]

| ^~~~~

/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_2/task_61/b7_s3_fused_rg_no_divergence/base/base.cu:15:31: note: the last parameter in the range is 'beta'

15 | const float* __restrict__ beta, // GroupNorm bias, shape: [C]

| ^~~~

/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_2/task_61/b7_s3_fused_rg_no_divergence/base/base.cu:16:5: warning: 3 adjacent parameters of 'fused_relu_groupnorm_no_div_kernel' of similar type ('int') are easily swapped by mistake [bugprone-easily-swappable-parameters]