import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
linear_weight: torch.Tensor,
linear_bias: torch.Tensor,
constant: torch.Tensor,
) -> torch.Tensor:
"""
Performs matrix multiplication, applies minimum with constant, and subtracts constant.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, in_features)
linear_weight (torch.Tensor): Weight matrix of shape (out_features, in_features)
linear_bias (torch.Tensor): Bias vector of shape (out_features)
constant (torch.Tensor): Scalar constant tensor
Returns:
torch.Tensor: Output tensor of shape (batch_size, out_features)
"""
x = F.linear(x, linear_weight, linear_bias)
x = torch.min(x, constant)
x = x - constant
return x
class Model(nn.Module):
"""
Simple model that performs a matrix multiplication, applies minimum, and subtracts a constant.
"""
def __init__(self, in_features, out_features, constant):
super(Model, self).__init__()
gemm = nn.Linear(in_features, out_features)
self.linear_weight = nn.Parameter(gemm.weight)
self.linear_bias = nn.Parameter(gemm.bias)
self.constant = nn.Parameter(torch.tensor(constant))
def forward(self, x, fn=module_fn):
return fn(x, self.linear_weight, self.linear_bias, self.constant)
batch_size = 128
in_features = 10
out_features = 5
constant = 2.0
def get_inputs():
return [torch.randn(batch_size, in_features)]
def get_init_inputs():
return [in_features, out_features, constant]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Simple model that performs a matrix multiplication, applies minimum, and subtracts a constant.
"""
def __init__(self, in_features, out_features, constant):
super(Model, self).__init__()
self.linear = nn.Linear(in_features, out_features)
self.constant = nn.Parameter(torch.tensor(constant))
def forward(self, x):
x = self.linear(x)
x = torch.min(x, self.constant)
x = x - self.constant
return x
batch_size = 128
in_features = 10
out_features = 5
constant = 2.0
def get_inputs():
return [torch.randn(batch_size, in_features)]
def get_init_inputs():
return [in_features, out_features, constant]#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define WARP_SIZE 32
// Each block computes one dot product for (batch_idx, out_idx)
// ensuring memory coalescing by having threads in the warp load consecutive elements
// from the input row of x and the corresponding row of linear_weight.
__global__ void my_kernel(
const float* x,
const float* linear_weight,
const float* linear_bias,
const float* constant,
float* y,
int batch_size,
int in_features,
int out_features) {
// Map each block to one output element for one batch element
int index = blockIdx.x; // index over (batch * out_features)
int batch_idx = index / out_features;
int out_idx = index % out_features;
float sum = 0.0f;
// Each thread in the block (warp) processes a portion of the dot product
for (int i = threadIdx.x; i < in_features; i += blockDim.x) {
// Coalesced read: threads in warp read consecutive elements
float a = x[batch_idx * in_features + i];
float b = linear_weight[out_idx * in_features + i];
sum += a * b;
}
// Warp-level reduction using __shfl_down_sync
for (int offset = WARP_SIZE / 2; offset > 0; offset /= 2) {
sum += __shfl_down_sync(0xffffffff, sum, offset);
}
if (threadIdx.x == 0) {
float result = sum + linear_bias[out_idx];
float c = *constant;
result = (result > c) ? c : result;
y[batch_idx * out_features + out_idx] = result - c;
}
}
// Pybind11 binding
torch::Tensor forward(
torch::Tensor x,
torch::Tensor linear_weight,
torch::Tensor linear_bias,
torch::Tensor constant) {
TORCH_CHECK(x.is_cuda(), "x must be a CUDA tensor");
TORCH_CHECK(linear_weight.is_cuda(), "linear_weight must be a CUDA tensor");
TORCH_CHECK(linear_bias.is_cuda(), "linear_bias must be a CUDA tensor");
TORCH_CHECK(constant.is_cuda(), "constant must be a CUDA tensor");
int batch_size = x.size(0);
int in_features = x.size(1);
int out_features = linear_weight.size(0);
auto y = torch::zeros({batch_size, out_features}, x.options());
const float* x_ptr = x.data_ptr<float>();
const float* weight_ptr = linear_weight.data_ptr<float>();
const float* bias_ptr = linear_bias.data_ptr<float>();
const float* constant_ptr = constant.data_ptr<float>();
float* y_ptr = y.data_ptr<float>();
// Launch one block per (batch element, out_feature) pair.
int total_blocks = batch_size * out_features;
int threads = WARP_SIZE; // 32 threads per block to form a full warp
my_kernel<<<total_blocks, threads>>>(
x_ptr,
weight_ptr,
bias_ptr,
constant_ptr,
y_ptr,
batch_size,
in_features,
out_features);
return y;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &forward, "CUDA forward function");
}
| Metric | Value | Unit | Variance | Samples |
|---|---|---|---|---|
| Executed Ipc Active | 0.168 | inst/cycle | 0.000 | 5 |
| Executed Ipc Elapsed | 0.060 | inst/cycle | 0.000 | 5 |
| Issue Slots Busy | 4.354 | % | 0.058 | 5 |
| Issued Ipc Active | 0.176 | inst/cycle | 0.000 | 5 |
| SM Busy | 4.354 | % | 0.058 | 5 |
| Memory Throughput | 2381934524.468 | byte/second | 4245421091459995.000 | 5 |
| Mem Busy | 8.566 | % | 0.049 | 5 |
| Max Bandwidth | 4.624 | % | 0.019 | 5 |
| L1/TEX Hit Rate | 34.040 | % | 0.000 | 5 |
| L2 Hit Rate | 101.044 | % | 0.033 | 5 |
| Mem Pipes Busy | 2.066 | % | 0.003 | 5 |
| Warp Cycles Per Issued Instruction | 27.278 | cycle | 9.348 | 5 |
| Warp Cycles Per Executed Instruction | 28.696 | cycle | 10.330 | 5 |
| Avg. Active Threads Per Warp | 21.550 | 0.000 | 5 | |
| Avg. Not Predicated Off Threads Per Warp | 19.360 | 0.000 | 5 | |
| Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
| Max Cluster Size | 8.000 | block | 0.000 | 5 |
| Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
| Cluster Occupancy | 0.000 | % | 0.000 | 5 |
| Block Limit SM | 32.000 | block | 0.000 | 5 |
| Block Limit Registers | 84.000 | block | 0.000 | 5 |
| Block Limit Shared Mem | 32.000 | block | 0.000 | 5 |
| Block Limit Warps | 64.000 | block | 0.000 | 5 |
| Theoretical Active Warps per SM | 32.000 | warp | 0.000 | 5 |
| Theoretical Occupancy | 50.000 | % | 0.000 | 5 |
| Achieved Occupancy | 7.408 | % | 0.000 | 5 |
| Achieved Active Warps Per SM | 4.740 | warp | 0.000 | 5 |
| Rule | Description |
|---|---|
| WRN HighPipeUtilization | All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details. |
| INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
| WRN ThreadDivergence | Instructions are executed in warps, which are groups of 32 threads. Optimal instruction throughput is achieved if all 32 threads of a warp execute the same instruction. The chosen launch configuration, early thread completion, and divergent flow control can significantly lower the number of active threads in a warp per cycle. This kernel achieves an average of 21.5 threads being active per cycle. This is further reduced to 19.4 threads per warp due to predication. The compiler may use predication to avoid an actual branch. Instead, all instructions are scheduled, but a per-thread condition code or predicate controls which threads execute the instructions. Try to avoid different execution paths within a warp when possible. In addition, ensure your kernel makes use of Independent Thread Scheduling, which allows a warp to reconverge after a data-dependent conditional block by explicitly calling __syncwarp(). |
| WRN Occupancy | This kernel's theoretical occupancy (50.0%) is limited by the number of blocks that can fit on the SM. This kernel's theoretical occupancy (50.0%) is limited by the required amount of shared memory. The difference between calculated theoretical (50.0%) and measured achieved occupancy (7.4%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
| Operation / Metric | Value | Unit |
|---|---|---|
| aten::to | ||
| CPU Time | 512944.01 | μs |
| Device Time | 6.81 | μs |
| Self CPU Time | 64.42 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zeros | ||
| CPU Time | 5930653.89 | μs |
| Device Time | 223219.45 | μs |
| Self CPU Time | 145258.12 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zero_ | ||
| CPU Time | 6280769.95 | μs |
| Device Time | 7989081.05 | μs |
| Self CPU Time | 343780.05 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::fill_ | ||
| CPU Time | 5936994.10 | μs |
| Device Time | 7989081.05 | μs |
| Self CPU Time | 411470.40 | μs |
| Self Device Time | 7989081.05 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaLaunchKernel | ||
| CPU Time | 5922376.47 | μs |
| Device Time | 2933.11 | μs |
| Self CPU Time | 5922376.47 | μs |
| Self Device Time | 2933.11 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| my_kernel(float const*, float const*, float const*, float const*, float*, int, int, int) | ||
| CPU Time | 0.00 | μs |
| Device Time | 341859.96 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 341859.96 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaEventRecord | ||
| CPU Time | 269770.50 | μs |
| Device Time | 1288054.01 | μs |
| Self CPU Time | 269770.50 | μs |
| Self Device Time | 1288054.01 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>) | ||
| CPU Time | 0.00 | μs |
| Device Time | 7765861.60 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 7765861.60 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
45289 warnings generated when compiling for host. Suppressed 45324 warnings (45277 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.