← Back to Leaderboard

The AI CUDA Engineer 👷

33_VanillaRNNefficient_concat_base

Level 3 • Task 33
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(
    x: torch.Tensor,
    i2h_weight: torch.Tensor,
    i2h_bias: torch.Tensor,
    h2o_weight: torch.Tensor,
    h2o_bias: torch.Tensor,
    hidden: torch.Tensor,
) -> torch.Tensor:
    """
    Vanilla RNN forward pass

    Args:
        x: Input tensor of shape (batch_size, input_size)
        i2h_weight: Weight tensor for input-to-hidden layer
        i2h_bias: Bias tensor for input-to-hidden layer
        h2o_weight: Weight tensor for hidden-to-output layer
        h2o_bias: Bias tensor for hidden-to-output layer
        hidden: Hidden state tensor

    Returns:
        Output tensor of shape (batch_size, output_size)
    """
    hidden = hidden.to(x.device)
    combined = torch.cat((x, hidden), dim=1)
    hidden = torch.tanh(F.linear(combined, i2h_weight, i2h_bias))
    output = F.linear(hidden, h2o_weight, h2o_bias)
    return output


class Model(nn.Module):
    def __init__(self, input_size: int, hidden_size: int, output_size: int):
        """
        Initialize the Vanilla RNN model.

        :param input_size: The number of input features (int).
        :param hidden_size: The size of the hidden state (int).
        :param output_size: The number of output features (int).
        """
        super(Model, self).__init__()
        self.input_size = input_size
        self.hidden_size = hidden_size
        self.output_size = output_size
        self.hidden = nn.Parameter(torch.randn((batch_size, hidden_size)))

        # Extract parameters from linear layers
        i2h = nn.Linear(input_size + hidden_size, hidden_size)
        self.i2h_weight = nn.Parameter(i2h.weight.data.clone())
        self.i2h_bias = nn.Parameter(i2h.bias.data.clone())

        h2o = nn.Linear(hidden_size, output_size)
        self.h2o_weight = nn.Parameter(h2o.weight.data.clone())
        self.h2o_bias = nn.Parameter(h2o.bias.data.clone())

    def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
        return fn(
            x,
            self.i2h_weight,
            self.i2h_bias,
            self.h2o_weight,
            self.h2o_bias,
            self.hidden,
        )


batch_size = 8
input_size = 1024
hidden_size = 256
output_size = 128
sequence_length = 256


def get_inputs():
    return [torch.randn(batch_size, input_size)]


def get_init_inputs():
    return [input_size, hidden_size, output_size]
import torch
import torch.nn as nn

class Model(nn.Module):
    def __init__(self, input_size: int, hidden_size: int, output_size: int):
        """
        Initialize the Vanilla RNN model.
        
        :param input_size: The number of input features (int).
        :param hidden_size: The size of the hidden state (int).
        :param output_size: The number of output features (int).
        """
        super(Model, self).__init__()
        self.input_size = input_size
        self.hidden_size = hidden_size
        self.output_size = output_size
        self.hidden = torch.randn((batch_size, hidden_size))
        
        # Define the RNN cell components (input to hidden, hidden to hidden, and hidden to output)
        self.i2h = nn.Linear(input_size + hidden_size, hidden_size)  # Input to hidden
        self.h2o = nn.Linear(hidden_size, output_size)  # Hidden to output
        self.tanh = nn.Tanh()  # Activation function for hidden state
    
    def forward(self, x: torch.Tensor) -> torch.Tensor:
        """
        Forward pass of the Vanilla RNN.
        
        :param x: Input tensor of shape (batch_size, input_size).
        :param hidden: Hidden state tensor of shape (batch_size, hidden_size).
        :return: Output tensor of shape (batch_size, output_size), and the new hidden state.
        """
        self.hidden = self.hidden.to(x.device)
        combined = torch.cat((x, self.hidden), dim=1)  # Concatenate input and hidden state
        self.hidden = self.tanh(self.i2h(combined))  # Update hidden state
        output = self.h2o(self.hidden)  # Compute output
        return output

batch_size = 8
input_size = 1024
hidden_size = 256
output_size = 128
sequence_length = 256

def get_inputs():
    return [torch.randn(batch_size, input_size)]

def get_init_inputs():
    return [input_size, hidden_size, output_size]

Kernel Information

Related Kernels (Level 3, Task 33 • 33_VanillaRNN)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 fused_rnn_i2h_warp_base 0.02 1.21 2.67
🥈 warp_optimized_rnn_base 0.02 1.15 2.56
🥈 optimized_rnn_reduction_base 0.02 1.15 2.56
4 atomic_rnn_optimized_edit_1 0.02 1.11 2.45
4 modular_warp_rnn_base 0.02 1.11 2.45
6 balanced_load_rnn_base_base 0.03 0.83 1.84
6 optimized_concat_kernel_base 0.03 0.83 1.84
6 optimized_unroll_concat_base 0.03 0.83 1.84
6 shared_memory_optimized_edit_1 0.03 0.83 1.84
6 stride_loops_rnn_base 0.03 0.83 1.84
6 optimal_blocksize_rnn_edit_1 0.03 0.83 1.84
6 modular_vanillarnn_edit_1 0.03 0.83 1.84
6 unroll_optimized_rnn_base_base 0.03 0.83 1.84
6 optimized_concat_base 0.03 0.83 1.84
15 unrolled_rnn_base_base 0.03 0.80 1.78
15 efficient_concat_base 0.03 0.80 1.78
15 sync_optimized_rnn_base_base 0.03 0.80 1.78
15 atomic_optimized_rnn_base 0.03 0.80 1.78
15 warp_aligned_rnn_base 0.03 0.80 1.78
15 optimized_concat_kernel_edit_1 0.03 0.80 1.78
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>

#define BLOCK_SIZE 256

// This kernel combines the concatenation of two tensors in one pass using a grid-stride loop
// and conditional assignment. It leverages loop unrolling where possible for improved performance.
__global__ void efficient_concat_kernel(
    const float* __restrict__ x,
    const float* __restrict__ hidden,
    float* __restrict__ combined,
    int batch_size,
    int x_size,
    int hidden_size
) {
    const int total_cols = x_size + hidden_size;
    const int total_elements = batch_size * total_cols;
    
    // Grid-stride loop to cover all elements
    for (int idx = blockIdx.x * blockDim.x + threadIdx.x;
         idx < total_elements;
         idx += gridDim.x * blockDim.x) {
        int row = idx / total_cols;
        int col = idx % total_cols;
        // Use branch to select source tensor
        combined[idx] = (col < x_size) ? x[row * x_size + col] : hidden[row * hidden_size + (col - x_size)];
    }
}

// Module function wrapping the kernel call and PyTorch operations
torch::Tensor module_fn_cuda(
    torch::Tensor x,
    torch::Tensor i2h_weight,
    torch::Tensor i2h_bias,
    torch::Tensor h2o_weight,
    torch::Tensor h2o_bias,
    torch::Tensor hidden
) {
    // Ensure tensors are contiguous and on CUDA
    x = x.contiguous().cuda();
    i2h_weight = i2h_weight.contiguous().cuda();
    i2h_bias = i2h_bias.contiguous().cuda();
    h2o_weight = h2o_weight.contiguous().cuda();
    h2o_bias = h2o_bias.contiguous().cuda();
    hidden = hidden.contiguous().cuda();

    const int batch_size = x.size(0);
    const int x_size = x.size(1);
    const int hidden_size = hidden.size(1);

    auto options = torch::TensorOptions().dtype(x.dtype()).device(x.device());
    torch::Tensor combined = torch::empty({batch_size, x_size + hidden_size}, options);

    const int total_elements = batch_size * (x_size + hidden_size);
    const int blocks = (total_elements + BLOCK_SIZE - 1) / BLOCK_SIZE;

    efficient_concat_kernel<<<blocks, BLOCK_SIZE>>>(
        x.data_ptr<float>(),
        hidden.data_ptr<float>(),
        combined.data_ptr<float>(),
        batch_size,
        x_size,
        hidden_size
    );

    // Compute activated hidden state and final output
    torch::Tensor hidden_new = torch::tanh(torch::addmm(i2h_bias, combined, i2h_weight.t()));
    torch::Tensor output = torch::addmm(h2o_bias, hidden_new, h2o_weight.t());

    return output;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &module_fn_cuda, "Module forward (CUDA)");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 0.310 inst/cycle 0.000 5
Executed Ipc Elapsed 0.030 inst/cycle 0.000 5
Issue Slots Busy 8.264 % 0.122 5
Issued Ipc Active 0.332 inst/cycle 0.000 5
SM Busy 8.264 % 0.122 5
Memory Throughput 13873449945.570 byte/second 444447912022804096.000 5
Mem Busy 10.074 % 0.244 5
Max Bandwidth 5.420 % 0.066 5
L1/TEX Hit Rate 0.000 % 0.000 5
L2 Hit Rate 98.056 % 0.003 5
Mem Pipes Busy 0.868 % 0.002 5
Warp Cycles Per Issued Instruction 23.104 cycle 0.108 5
Warp Cycles Per Executed Instruction 24.620 cycle 0.121 5
Avg. Active Threads Per Warp 32.000 0.000 5
Avg. Not Predicated Off Threads Per Warp 25.920 0.000 5
Max Active Clusters 0.000 cluster 0.000 5
Max Cluster Size 8.000 block 0.000 5
Overall GPU Occupancy 0.000 % 0.000 5
Cluster Occupancy 0.000 % 0.000 5
Block Limit SM 32.000 block 0.000 5
Block Limit Registers 10.000 block 0.000 5
Block Limit Shared Mem 32.000 block 0.000 5
Block Limit Warps 8.000 block 0.000 5
Theoretical Active Warps per SM 64.000 warp 0.000 5
Theoretical Occupancy 100.000 % 0.000 5
Achieved Occupancy 12.192 % 0.018 5
Achieved Active Warps Per SM 7.804 warp 0.007 5
Analysis Rules
Rule Description
WRN HighPipeUtilization All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (12.0%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
Operation / Metric Value Unit
aten::to
CPU Time 411663.25 μs
Device Time 66.59 μs
Self CPU Time 34944.40 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 376718.86 μs
Device Time 66.59 μs
Self CPU Time 126.86 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::empty_strided
CPU Time 376181.82 μs
Device Time 0.00 μs
Self CPU Time 161.62 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaDeviceGetStreamPriorityRange
CPU Time 375400.74 μs
Device Time 0.00 μs
Self CPU Time 375400.74 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::addmm
CPU Time 789917.91 μs
Device Time 329612.68 μs
Self CPU Time 452428.05 μs
Self Device Time 329612.68 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
sm80_xmma_gemm_f32f32_f32f32_f32_tn_n_tilesize32x32x8_stage3_warpsize1x2x1_ffma_aligna4_alignc4_execute_kernel__51_cublas
CPU Time 0.00 μs
Device Time 165093.23 μs
Self CPU Time 0.00 μs
Self Device Time 165093.23 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 115459.78 μs
Device Time 1088096.22 μs
Self CPU Time 25625.56 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 89836.07 μs
Device Time 1088096.22 μs
Self CPU Time 31444.25 μs
Self Device Time 1088096.22 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 1088096.22 μs
Self CPU Time 0.00 μs
Self Device Time 1088096.22 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Completed
45285 warnings generated when compiling for host.
Suppressed 45326 warnings (45279 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:13:5 bugprone-easily-swappable-parameters
13 | int batch_size,
| ^~~~~~~~~~~~~~~
14 | int x_size,
| ~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:13:9: note: the first parameter in the range is 'batch_size'
13 | int batch_size,
| ^~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:14:9: note: the last parameter in the range is 'x_size'
14 | int x_size,
| ^~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:21:20: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
21 | for (int idx = blockIdx.x * blockDim.x + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:23:17: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
23 | idx += gridDim.x * blockDim.x) {
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:48:28: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
48 | const int batch_size = x.size(0);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:49:24: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
49 | const int x_size = x.size(1);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250204_optimize_b10_s4_e0_sweep/level_3/task_33/b4_s1_efficient_concat/base/base.cu:50:29: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
50 | const int hidden_size = hidden.size(1);
| ^