import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor,
i2h_weight: torch.Tensor,
i2h_bias: torch.Tensor,
h2o_weight: torch.Tensor,
h2o_bias: torch.Tensor,
hidden: torch.Tensor,
) -> torch.Tensor:
"""
Vanilla RNN forward pass
Args:
x: Input tensor of shape (batch_size, input_size)
i2h_weight: Weight tensor for input-to-hidden layer
i2h_bias: Bias tensor for input-to-hidden layer
h2o_weight: Weight tensor for hidden-to-output layer
h2o_bias: Bias tensor for hidden-to-output layer
hidden: Hidden state tensor
Returns:
Output tensor of shape (batch_size, output_size)
"""
hidden = hidden.to(x.device)
combined = torch.cat((x, hidden), dim=1)
hidden = torch.tanh(F.linear(combined, i2h_weight, i2h_bias))
output = F.linear(hidden, h2o_weight, h2o_bias)
return output
class Model(nn.Module):
def __init__(self, input_size: int, hidden_size: int, output_size: int):
"""
Initialize the Vanilla RNN model.
:param input_size: The number of input features (int).
:param hidden_size: The size of the hidden state (int).
:param output_size: The number of output features (int).
"""
super(Model, self).__init__()
self.input_size = input_size
self.hidden_size = hidden_size
self.output_size = output_size
self.hidden = nn.Parameter(torch.randn((batch_size, hidden_size)))
# Extract parameters from linear layers
i2h = nn.Linear(input_size + hidden_size, hidden_size)
self.i2h_weight = nn.Parameter(i2h.weight.data.clone())
self.i2h_bias = nn.Parameter(i2h.bias.data.clone())
h2o = nn.Linear(hidden_size, output_size)
self.h2o_weight = nn.Parameter(h2o.weight.data.clone())
self.h2o_bias = nn.Parameter(h2o.bias.data.clone())
def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
return fn(
x,
self.i2h_weight,
self.i2h_bias,
self.h2o_weight,
self.h2o_bias,
self.hidden,
)
batch_size = 8
input_size = 1024
hidden_size = 256
output_size = 128
sequence_length = 256
def get_inputs():
return [torch.randn(batch_size, input_size)]
def get_init_inputs():
return [input_size, hidden_size, output_size]
import torch
import torch.nn as nn
class Model(nn.Module):
def __init__(self, input_size: int, hidden_size: int, output_size: int):
"""
Initialize the Vanilla RNN model.
:param input_size: The number of input features (int).
:param hidden_size: The size of the hidden state (int).
:param output_size: The number of output features (int).
"""
super(Model, self).__init__()
self.input_size = input_size
self.hidden_size = hidden_size
self.output_size = output_size
self.hidden = torch.randn((batch_size, hidden_size))
# Define the RNN cell components (input to hidden, hidden to hidden, and hidden to output)
self.i2h = nn.Linear(input_size + hidden_size, hidden_size) # Input to hidden
self.h2o = nn.Linear(hidden_size, output_size) # Hidden to output
self.tanh = nn.Tanh() # Activation function for hidden state
def forward(self, x: torch.Tensor) -> torch.Tensor:
"""
Forward pass of the Vanilla RNN.
:param x: Input tensor of shape (batch_size, input_size).
:param hidden: Hidden state tensor of shape (batch_size, hidden_size).
:return: Output tensor of shape (batch_size, output_size), and the new hidden state.
"""
self.hidden = self.hidden.to(x.device)
combined = torch.cat((x, self.hidden), dim=1) # Concatenate input and hidden state
self.hidden = self.tanh(self.i2h(combined)) # Update hidden state
output = self.h2o(self.hidden) # Compute output
return output
batch_size = 8
input_size = 1024
hidden_size = 256
output_size = 128
sequence_length = 256
def get_inputs():
return [torch.randn(batch_size, input_size)]
def get_init_inputs():
return [input_size, hidden_size, output_size]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define BLOCK_SIZE 256
// Kernel that concatenates x and hidden into combined with shared memory optimization
__global__ void concat_kernel_shared(
const float* __restrict__ x,
const float* __restrict__ hidden,
float* __restrict__ combined,
const int batch_size,
const int x_size,
const int hidden_size
) {
extern __shared__ float shared_mem[];
const int total_width = x_size + hidden_size;
// 2D grid mapping: blockIdx.y for batch dimension, blockIdx.x for width dimension
const int tid = threadIdx.x;
const int row = blockIdx.y;
const int col_base = blockIdx.x * blockDim.x;
const int col = col_base + tid;
if (row < batch_size && col < total_width) {
const int idx = row * total_width + col;
if (col < x_size) {
shared_mem[tid] = x[row * x_size + col];
} else {
shared_mem[tid] = hidden[row * hidden_size + (col - x_size)];
}
__syncthreads();
combined[idx] = shared_mem[tid];
}
}
torch::Tensor module_fn_cuda(
torch::Tensor x,
torch::Tensor i2h_weight,
torch::Tensor i2h_bias,
torch::Tensor h2o_weight,
torch::Tensor h2o_bias,
torch::Tensor hidden
) {
// Ensure that all tensors are contiguous
x = x.contiguous();
i2h_weight = i2h_weight.contiguous();
i2h_bias = i2h_bias.contiguous();
h2o_weight = h2o_weight.contiguous();
h2o_bias = h2o_bias.contiguous();
hidden = hidden.contiguous();
const int batch_size = x.size(0);
const int x_size = x.size(1);
const int hidden_size = hidden.size(1);
int total_width = x_size + hidden_size;
auto options = torch::TensorOptions().dtype(x.dtype()).device(x.device());
auto combined = torch::empty({batch_size, total_width}, options);
int total_elements = batch_size * total_width;
int threads = BLOCK_SIZE;
int blocks = (total_elements + threads - 1) / threads;
if (blocks > 65535) {
blocks = 65535;
}
// Allocate shared memory dynamically
size_t shared_mem_size = threads * sizeof(float);
concat_kernel_shared<<<blocks, threads, shared_mem_size>>>(
x.data_ptr<float>(),
hidden.data_ptr<float>(),
combined.data_ptr<float>(),
batch_size,
x_size,
hidden_size
);
// Compute the new hidden state: tanh(linear(combined, i2h_weight, i2h_bias))
auto hidden_new = torch::tanh(torch::addmm(i2h_bias, combined, i2h_weight.t()));
// Compute the output: linear(hidden_new, h2o_weight, h2o_bias)
auto output = torch::addmm(h2o_bias, hidden_new, h2o_weight.t());
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &module_fn_cuda, "Module forward (CUDA)");
}
Metric | Value | Unit | Variance | Samples |
---|---|---|---|---|
Executed Ipc Active | 0.116 | inst/cycle | 0.000 | 5 |
Executed Ipc Elapsed | 0.010 | inst/cycle | 0.000 | 5 |
Issue Slots Busy | 3.434 | % | 0.153 | 5 |
Issued Ipc Active | 0.136 | inst/cycle | 0.000 | 5 |
SM Busy | 3.890 | % | 0.198 | 5 |
Memory Throughput | 2579210306.970 | byte/second | 3160415543021845.000 | 5 |
Mem Busy | 10.404 | % | 0.072 | 5 |
Max Bandwidth | 5.332 | % | 0.015 | 5 |
L1/TEX Hit Rate | 0.000 | % | 0.000 | 5 |
L2 Hit Rate | 100.664 | % | 0.313 | 5 |
Mem Pipes Busy | 0.868 | % | 0.000 | 5 |
Warp Cycles Per Issued Instruction | 55.892 | cycle | 34.695 | 5 |
Warp Cycles Per Executed Instruction | 67.732 | cycle | 50.984 | 5 |
Avg. Active Threads Per Warp | 32.000 | 0.000 | 5 | |
Avg. Not Predicated Off Threads Per Warp | 30.700 | 0.000 | 5 | |
Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
Max Cluster Size | 8.000 | block | 0.000 | 5 |
Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
Cluster Occupancy | 0.000 | % | 0.000 | 5 |
Block Limit SM | 32.000 | block | 0.000 | 5 |
Block Limit Registers | 16.000 | block | 0.000 | 5 |
Block Limit Shared Mem | 16.000 | block | 0.000 | 5 |
Block Limit Warps | 8.000 | block | 0.000 | 5 |
Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
Achieved Occupancy | 12.348 | % | 0.000 | 5 |
Achieved Active Warps Per SM | 7.904 | warp | 0.000 | 5 |
Rule | Description |
---|---|
WRN HighPipeUtilization | All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details. |
INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (12.3%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
Operation / Metric | Value | Unit |
---|---|---|
aten::to | ||
CPU Time | 294969.23 | μs |
Device Time | 70.66 | μs |
Self CPU Time | 64.99 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::_to_copy | ||
CPU Time | 294904.24 | μs |
Device Time | 70.66 | μs |
Self CPU Time | 125.58 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::empty_strided | ||
CPU Time | 294402.26 | μs |
Device Time | 0.00 | μs |
Self CPU Time | 136.35 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
cudaDeviceGetStreamPriorityRange | ||
CPU Time | 292531.05 | μs |
Device Time | 0.00 | μs |
Self CPU Time | 292531.05 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::addmm | ||
CPU Time | 800575.76 | μs |
Device Time | 319335.68 | μs |
Self CPU Time | 447053.97 | μs |
Self Device Time | 319335.68 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
sm80_xmma_gemm_f32f32_f32f32_f32_tn_n_tilesize32x32x8_stage3_warpsize1x2x1_ffma_aligna4_alignc4_execute_kernel__51_cublas | ||
CPU Time | 0.00 | μs |
Device Time | 158381.72 | μs |
Self CPU Time | 0.00 | μs |
Self Device Time | 158381.72 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::zero_ | ||
CPU Time | 115323.46 | μs |
Device Time | 1049386.49 | μs |
Self CPU Time | 29346.91 | μs |
Self Device Time | 0.00 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
aten::fill_ | ||
CPU Time | 85978.71 | μs |
Device Time | 1049386.49 | μs |
Self CPU Time | 30947.92 | μs |
Self Device Time | 1049386.49 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>) | ||
CPU Time | 0.00 | μs |
Device Time | 1049386.49 | μs |
Self CPU Time | 0.00 | μs |
Self Device Time | 1049386.49 | μs |
CPU Memory Usage | 0 | B |
Device Memory Usage | 0 | B |
Self CPU Memory Usage | 0 | B |
Self Device Memory Usage | 0 | B |
45287 warnings generated when compiling for host. Suppressed 45326 warnings (45279 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.