import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor, kernel_size: int, stride: int, padding: int
) -> torch.Tensor:
"""
Applies 2D Average Pooling using functional interface.
Args:
x (torch.Tensor): Input tensor
kernel_size (int): Size of pooling window
stride (int): Stride of pooling operation
padding (int): Input padding
Returns:
torch.Tensor: Output tensor with 2D Average Pooling applied
"""
return F.avg_pool2d(x, kernel_size=kernel_size, stride=stride, padding=padding)
class Model(nn.Module):
"""
Simple model that performs 2D Average Pooling.
"""
def __init__(self, kernel_size: int, stride: int, padding: int):
"""
Initializes the Average Pooling layer.
Args:
kernel_size (int): Size of the pooling window
stride (int): Stride of the pooling operation
padding (int): Padding applied to input tensor
"""
super(Model, self).__init__()
self.kernel_size = kernel_size
self.stride = stride
self.padding = padding
def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
"""
Applies 2D Average Pooling to the input tensor.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, channels, height, width)
fn: Function to apply pooling operation, defaults to module_fn
Returns:
torch.Tensor: Output tensor with Average Pooling applied
"""
return fn(
x,
self.kernel_size,
self.stride,
self.padding,
)
batch_size = 16
channels = 64
height = 256
width = 256
kernel_size = 3
stride = None # Defaults to kernel_size
padding = 0
def get_inputs():
x = torch.randn(batch_size, channels, height, width)
return [x]
def get_init_inputs():
return [kernel_size, stride if stride is not None else kernel_size, padding]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Simple model that performs 2D Average Pooling.
"""
def __init__(self, kernel_size: int, stride: int = None, padding: int = 0):
"""
Initializes the Average Pooling layer.
Args:
kernel_size (int): Size of the pooling window.
stride (int, optional): Stride of the pooling operation. Defaults to None (same as kernel_size).
padding (int, optional): Padding applied to the input tensor. Defaults to 0.
"""
super(Model, self).__init__()
self.avg_pool = nn.AvgPool2d(
kernel_size=kernel_size, stride=stride, padding=padding
)
def forward(self, x: torch.Tensor) -> torch.Tensor:
"""
Applies 2D Average Pooling to the input tensor.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, channels, height, width).
Returns:
torch.Tensor: Output tensor with Average Pooling applied.
"""
return self.avg_pool(x)
batch_size = 16
channels = 64
height = 256
width = 256
kernel_size = 3
stride = None # Defaults to kernel_size
padding = 0
def get_inputs():
x = torch.randn(batch_size, channels, height, width)
return [x]
def get_init_inputs():
return [kernel_size, stride if stride is not None else kernel_size, padding]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
// Kernel that uses a flat 1D grid-stride loop to evenly distribute workload among threads
template <typename scalar_t>
__global__ void even_workload_avg_pool2d_kernel(
const scalar_t* __restrict__ input,
scalar_t* __restrict__ output,
const int N,
const int C,
const int H,
const int W,
const int outH,
const int outW,
const int kernel_size,
const int stride,
const int padding
) {
int total = N * C * outH * outW;
int gridStride = blockDim.x * gridDim.x;
// Each thread handles multiple output elements via grid-stride loop
for (int idx = blockIdx.x * blockDim.x + threadIdx.x; idx < total; idx += gridStride) {
// Compute the output coordinates
int w_out = idx % outW;
int h_out = (idx / outW) % outH;
int c = (idx / (outW * outH)) % C;
int n = idx / (outW * outH * C);
// Calculate the corresponding top-left corner of the pooling window in input
int in_x = w_out * stride - padding;
int in_y = h_out * stride - padding;
scalar_t sum = static_cast<scalar_t>(0);
// Fast path for common 3x3 pooling when the entire window is within bounds
if (kernel_size == 3 && in_x >= 0 && in_y >= 0 && (in_x + 3) <= W && (in_y + 3) <= H) {
int base = (n * C + c) * H;
int row0 = base + in_y;
int row1 = row0 + 1;
int row2 = row0 + 2;
sum = input[row0 * W + in_x] + input[row0 * W + in_x + 1] + input[row0 * W + in_x + 2] +
input[row1 * W + in_x] + input[row1 * W + in_x + 1] + input[row1 * W + in_x + 2] +
input[row2 * W + in_x] + input[row2 * W + in_x + 1] + input[row2 * W + in_x + 2];
} else {
// Generic path: iterate over the pooling window with boundary checks
for (int ky = 0; ky < kernel_size; ++ky) {
int y = in_y + ky;
if (y < 0 || y >= H) continue;
int row_offset = ((n * C + c) * H + y) * W;
for (int kx = 0; kx < kernel_size; ++kx) {
int x = in_x + kx;
if (x < 0 || x >= W) continue;
sum += input[row_offset + x];
}
}
}
output[idx] = sum / static_cast<scalar_t>(kernel_size * kernel_size);
}
}
// Forward function exposed to PyTorch
torch::Tensor even_workload_avg_pool2d_forward(
torch::Tensor x,
int kernel_size,
int stride,
int padding
) {
TORCH_CHECK(x.dim() == 4, "Input must be a 4D tensor.");
int N = x.size(0);
int C = x.size(1);
int H = x.size(2);
int W = x.size(3);
// Compute output dimensions
int outH = (H + 2 * padding - kernel_size) / stride + 1;
int outW = (W + 2 * padding - kernel_size) / stride + 1;
auto x_cont = x.contiguous();
auto output = torch::empty({N, C, outH, outW}, x.options());
int total = N * C * outH * outW;
int threads = 256;
int blocks = (total + threads - 1) / threads;
AT_DISPATCH_FLOATING_TYPES(x.scalar_type(), "even_workload_avg_pool2d_kernel", ([&] {
even_workload_avg_pool2d_kernel<scalar_t><<<blocks, threads>>>(
x_cont.data_ptr<scalar_t>(),
output.data_ptr<scalar_t>(),
N, C, H, W,
outH, outW,
kernel_size, stride, padding
);
}));
cudaError_t err = cudaGetLastError();
TORCH_CHECK(err == cudaSuccess, "CUDA Error: ", cudaGetErrorString(err));
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &even_workload_avg_pool2d_forward, "Evenly Distributed Average Pooling forward (CUDA)");
}
| Metric | Value | Unit | Variance | Samples |
|---|---|---|---|---|
| Executed Ipc Active | 2.326 | inst/cycle | 0.001 | 5 |
| Executed Ipc Elapsed | 2.242 | inst/cycle | 0.000 | 5 |
| Issue Slots Busy | 58.226 | % | 0.276 | 5 |
| Issued Ipc Active | 2.330 | inst/cycle | 0.001 | 5 |
| SM Busy | 58.226 | % | 0.276 | 5 |
| Memory Throughput | 3013507503756.941 | byte/second | 77590038585423069184.000 | 5 |
| Mem Busy | 51.214 | % | 0.025 | 5 |
| Max Bandwidth | 89.922 | % | 0.067 | 5 |
| L1/TEX Hit Rate | 65.720 | % | 0.000 | 5 |
| L2 Hit Rate | 13.082 | % | 0.001 | 5 |
| Mem Pipes Busy | 25.350 | % | 0.010 | 5 |
| Warp Cycles Per Issued Instruction | 23.396 | cycle | 0.022 | 5 |
| Warp Cycles Per Executed Instruction | 23.416 | cycle | 0.022 | 5 |
| Avg. Active Threads Per Warp | 32.000 | 0.000 | 5 | |
| Avg. Not Predicated Off Threads Per Warp | 27.910 | 0.000 | 5 | |
| Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
| Max Cluster Size | 8.000 | block | 0.000 | 5 |
| Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
| Cluster Occupancy | 0.000 | % | 0.000 | 5 |
| Block Limit SM | 32.000 | block | 0.000 | 5 |
| Block Limit Registers | 8.000 | block | 0.000 | 5 |
| Block Limit Shared Mem | 32.000 | block | 0.000 | 5 |
| Block Limit Warps | 8.000 | block | 0.000 | 5 |
| Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
| Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
| Achieved Occupancy | 85.148 | % | 0.236 | 5 |
| Achieved Active Warps Per SM | 54.496 | warp | 0.098 | 5 |
| Rule | Description |
|---|---|
| INF HighPipeUtilization | ALU is the highest-utilized pipeline (40.1%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck. |
| INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
| WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (85.3%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
| Operation / Metric | Value | Unit |
|---|---|---|
| aten::randn | ||
| CPU Time | 462421.17 | μs |
| Device Time | 0.00 | μs |
| Self CPU Time | 82.19 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::normal_ | ||
| CPU Time | 462312.42 | μs |
| Device Time | 0.00 | μs |
| Self CPU Time | 462312.42 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaLaunchKernel | ||
| CPU Time | 1193136.55 | μs |
| Device Time | 57976.26 | μs |
| Self CPU Time | 1193136.55 | μs |
| Self Device Time | 57976.26 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void even_workload_avg_pool2d_kernel<float>(float const*, float*, int, int, int, int, int, int, int, int, int) | ||
| CPU Time | 0.00 | μs |
| Device Time | 795567.41 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 795567.41 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zero_ | ||
| CPU Time | 727917.43 | μs |
| Device Time | 593398.61 | μs |
| Self CPU Time | 12712.13 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::fill_ | ||
| CPU Time | 715207.83 | μs |
| Device Time | 593398.61 | μs |
| Self CPU Time | 15996.88 | μs |
| Self Device Time | 593398.61 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>) | ||
| CPU Time | 0.00 | μs |
| Device Time | 593398.61 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 593398.61 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
45288 warnings generated when compiling for host. Suppressed 45324 warnings (45277 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.