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45_Average_Pooling_2D • optimized_avg_pool2d_base

Level 1 • Task 45
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(
    x: torch.Tensor, kernel_size: int, stride: int, padding: int
) -> torch.Tensor:
    """
    Applies 2D Average Pooling using functional interface.

    Args:
        x (torch.Tensor): Input tensor
        kernel_size (int): Size of pooling window
        stride (int): Stride of pooling operation
        padding (int): Input padding

    Returns:
        torch.Tensor: Output tensor with 2D Average Pooling applied
    """
    return F.avg_pool2d(x, kernel_size=kernel_size, stride=stride, padding=padding)


class Model(nn.Module):
    """
    Simple model that performs 2D Average Pooling.
    """

    def __init__(self, kernel_size: int, stride: int, padding: int):
        """
        Initializes the Average Pooling layer.

        Args:
            kernel_size (int): Size of the pooling window
            stride (int): Stride of the pooling operation
            padding (int): Padding applied to input tensor
        """
        super(Model, self).__init__()
        self.kernel_size = kernel_size
        self.stride = stride
        self.padding = padding

    def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
        """
        Applies 2D Average Pooling to the input tensor.

        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, channels, height, width)
            fn: Function to apply pooling operation, defaults to module_fn

        Returns:
            torch.Tensor: Output tensor with Average Pooling applied
        """
        return fn(
            x,
            self.kernel_size,
            self.stride,
            self.padding,
        )


batch_size = 16
channels = 64
height = 256
width = 256
kernel_size = 3
stride = None  # Defaults to kernel_size
padding = 0


def get_inputs():
    x = torch.randn(batch_size, channels, height, width)
    return [x]


def get_init_inputs():
    return [kernel_size, stride if stride is not None else kernel_size, padding]

import torch
import torch.nn as nn


class Model(nn.Module):
    """
    Simple model that performs 2D Average Pooling.
    """

    def __init__(self, kernel_size: int, stride: int = None, padding: int = 0):
        """
        Initializes the Average Pooling layer.

        Args:
            kernel_size (int): Size of the pooling window.
            stride (int, optional): Stride of the pooling operation. Defaults to None (same as kernel_size).
            padding (int, optional): Padding applied to the input tensor. Defaults to 0.
        """
        super(Model, self).__init__()
        self.avg_pool = nn.AvgPool2d(
            kernel_size=kernel_size, stride=stride, padding=padding
        )

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        """
        Applies 2D Average Pooling to the input tensor.

        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, channels, height, width).

        Returns:
            torch.Tensor: Output tensor with Average Pooling applied.
        """
        return self.avg_pool(x)


batch_size = 16
channels = 64
height = 256
width = 256
kernel_size = 3
stride = None  # Defaults to kernel_size
padding = 0


def get_inputs():
    x = torch.randn(batch_size, channels, height, width)
    return [x]


def get_init_inputs():
    return [kernel_size, stride if stride is not None else kernel_size, padding]
Download Evaluation Download PyTorch Download CUDA Download Profiles

Kernel Information

Operation Name 45_Average_Pooling_2D
Level ID 1
Task ID 45
Kernel Name optimized_avg_pool2d_base
CUDA Speedup (Native) 1.833x
CUDA Speedup (Compile) 2.866x
CUDA Runtime 0.114 ms
PyTorch Runtime (Native) 0.209 ms
PyTorch Runtime (Compile) 0.327 ms
Correct True
Max Diff (vs. Reference) 0.000000
Model azure-gpt-4o-2024-08-06
Temperature 0.50
View Experiment Progress Details

Related Kernels (Level 1, Task 45 • 45_Average_Pooling_2D)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 unrolled_avg_pool2d_base 0.11 1.94 3.03
🥇 modular_avg_pool2d_base_base 0.11 1.94 3.03
🥇 grid_stride_manual_unroll_base 0.11 1.94 3.03
🥇 optimized_avg_pool2d_base 0.11 1.94 3.03
🥇 manual_unroll_avg_pool2d_base 0.11 1.94 3.03
🥇 efficient_avg_pool_base 0.11 1.94 3.03
🥇 constant_memory_avg_pool2d_base 0.11 1.94 3.03
🥇 even_workload_avg_pool2d_base 0.11 1.94 3.03
🥇 unrolled_optimized_avg_pool2d_base 0.11 1.94 3.03
10 warp_uniform_flow_base_base 0.11 1.83 2.87
10 optimized_avg_pool2d_base 0.11 1.83 2.87
10 grid_stride_avg_pool2d_base_base 0.11 1.83 2.87
10 warp_uniform_flow_base_edit_1 0.11 1.83 2.87
14 stride_optimized_avg_pool2d_base 0.12 1.82 2.84
14 warp_divergence_avg_pool2d_base 0.12 1.82 2.84
14 stride_loop_avg_pool2d_base 0.12 1.82 2.84
14 grid_unrolled_avg_pool2d_base 0.12 1.82 2.84
18 combined_avg_pool_base 0.12 1.80 2.82
18 spatial_block_optimized_base_base 0.12 1.80 2.82
18 spatial_block_optimized_base_edit_1 0.12 1.80 2.82 
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>

// This kernel combines manual unrolling for common cases with grid-stride looping for efficiency
// and uses template specialization for compile-time optimizations.
template <typename scalar_t, int KERNEL_SIZE=0>
__global__ void optimized_avg_pool2d_kernel(
    const scalar_t* __restrict__ input,
    scalar_t* __restrict__ output,
    const int N,
    const int C,
    const int H,
    const int W,
    const int outH,
    const int outW,
    const int stride,
    const int padding,
    const int actual_kernel_size
) {
    const int total_elements = N * C * outH * outW;
    const int grid_stride = blockDim.x * gridDim.x;
    const float inv_window_size = 1.0f / (actual_kernel_size * actual_kernel_size);

    for (int idx = blockIdx.x * blockDim.x + threadIdx.x; 
         idx < total_elements; 
         idx += grid_stride) {
        const int w_out = idx % outW;
        const int h_out = (idx / outW) % outH;
        const int c = (idx / (outW * outH)) % C;
        const int n = idx / (outW * outH * C);

        const int h_start = h_out * stride - padding;
        const int w_start = w_out * stride - padding;
        
        float sum = 0.0f;

        if (KERNEL_SIZE == 3) {
            // Manual unrolling for 3x3 kernel size
            #pragma unroll
            for (int kh = 0; kh < 3; ++kh) {
                const int h = h_start + kh;
                if (h >= 0 && h < H) {
                    const int row_offset = ((n * C + c) * H + h) * W;
                    #pragma unroll
                    for (int kw = 0; kw < 3; ++kw) {
                        const int w = w_start + kw;
                        if (w >= 0 && w < W) {
                            sum += input[row_offset + w];
                        }
                    }
                }
            }
        } else {
            // Generic case for other kernel sizes
            const int h_clamp_start = max(0, h_start);
            const int w_clamp_start = max(0, w_start);
            const int h_clamp_end = min(H, h_start + actual_kernel_size);
            const int w_clamp_end = min(W, w_start + actual_kernel_size);

            for (int h = h_clamp_start; h < h_clamp_end; ++h) {
                const int row_offset = ((n * C + c) * H + h) * W;
                for (int w = w_clamp_start; w < w_clamp_end; ++w) {
                    sum += input[row_offset + w];
                }
            }
        }

        output[idx] = sum * inv_window_size;
    }
}

torch::Tensor optimized_avg_pool2d_forward(
    torch::Tensor x,
    int kernel_size,
    int stride,
    int padding
) {
    TORCH_CHECK(x.dim() == 4, "Input must be a 4D tensor.");
    
    const int N = x.size(0);
    const int C = x.size(1);
    const int H = x.size(2);
    const int W = x.size(3);
    
    const int outH = (H + 2 * padding - kernel_size) / stride + 1;
    const int outW = (W + 2 * padding - kernel_size) / stride + 1;
    
    auto x_cont = x.contiguous();
    auto out = torch::empty({N, C, outH, outW}, x.options());

    const int total = N * C * outH * outW;
    const int threads = 256;
    const int blocks = (total + threads - 1) / threads;

    AT_DISPATCH_FLOATING_TYPES(x.scalar_type(), "optimized_avg_pool2d", [&] {
        if (kernel_size == 3) {
            optimized_avg_pool2d_kernel<scalar_t, 3><<<blocks, threads>>>(
                x_cont.data_ptr<scalar_t>(),
                out.data_ptr<scalar_t>(),
                N, C, H, W,
                outH, outW,
                stride, padding,
                kernel_size
            );
        } else {
            optimized_avg_pool2d_kernel<scalar_t, 0><<<blocks, threads>>>(
                x_cont.data_ptr<scalar_t>(),
                out.data_ptr<scalar_t>(),
                N, C, H, W,
                outH, outW,
                stride, padding,
                kernel_size
            );
        }
    });

    cudaError_t err = cudaGetLastError();
    TORCH_CHECK(err == cudaSuccess, "CUDA Error: ", cudaGetErrorString(err));
    
    return out;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &optimized_avg_pool2d_forward, "Optimized 2D Average Pooling forward (CUDA)");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 2.454 inst/cycle 0.000 5
Executed Ipc Elapsed 2.372 inst/cycle 0.000 5
Issue Slots Busy 61.484 % 0.163 5
Issued Ipc Active 2.460 inst/cycle 0.000 5
SM Busy 61.484 % 0.163 5
Memory Throughput 2749927975073.298 byte/second 3948253281197645824.000 5
Mem Busy 46.672 % 0.001 5
Max Bandwidth 82.062 % 0.003 5
L1/TEX Hit Rate 65.720 % 0.000 5
L2 Hit Rate 13.192 % 0.000 5
Mem Pipes Busy 23.026 % 0.001 5
Warp Cycles Per Issued Instruction 21.904 cycle 0.007 5
Warp Cycles Per Executed Instruction 21.924 cycle 0.007 5
Avg. Active Threads Per Warp 32.000 0.000 5
Avg. Not Predicated Off Threads Per Warp 28.060 0.000 5
Max Active Clusters 0.000 cluster 0.000 5
Max Cluster Size 8.000 block 0.000 5
Overall GPU Occupancy 0.000 % 0.000 5
Cluster Occupancy 0.000 % 0.000 5
Block Limit SM 32.000 block 0.000 5
Block Limit Registers 8.000 block 0.000 5
Block Limit Shared Mem 32.000 block 0.000 5
Block Limit Warps 8.000 block 0.000 5
Theoretical Active Warps per SM 64.000 warp 0.000 5
Theoretical Occupancy 100.000 % 0.000 5
Achieved Occupancy 84.906 % 0.001 5
Achieved Active Warps Per SM 54.342 warp 0.001 5
Analysis Rules
Rule Description
INF HighPipeUtilization ALU is the highest-utilized pipeline (45.6%) based on active cycles, taking into account the rates of its different instructions. It executes integer and logic operations. It is well-utilized, but should not be a bottleneck.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (84.8%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
Operation / Metric Value Unit
aten::to
CPU Time 352388.44 μs
Device Time 28585.64 μs
Self CPU Time 53.71 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 352334.73 μs
Device Time 28585.64 μs
Self CPU Time 128.26 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaLaunchKernel
CPU Time 1208956.38 μs
Device Time 57103.23 μs
Self CPU Time 1208956.38 μs
Self Device Time 57103.23 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void optimized_avg_pool2d_kernel<float, 3>(float const*, float*, int, int, int, int, int, int, int, int, int)
CPU Time 0.00 μs
Device Time 836392.64 μs
Self CPU Time 0.00 μs
Self Device Time 836392.64 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 758413.31 μs
Device Time 584457.44 μs
Self CPU Time 13123.31 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 745291.72 μs
Device Time 584457.44 μs
Self CPU Time 15969.60 μs
Self Device Time 584457.44 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 584457.44 μs
Self CPU Time 0.00 μs
Self Device Time 584457.44 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Completed 
45290 warnings generated when compiling for host.
Suppressed 45324 warnings (45277 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:14:5 bugprone-easily-swappable-parameters
14 | const int W,
| ^~~~~~~~~~~~
15 | const int outH,
| ~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:14:15: note: the first parameter in the range is 'W'
14 | const int W,
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:15:15: note: the last parameter in the range is 'outH'
15 | const int outH,
| ^~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:16:5: warning: 2 adjacent parameters of 'optimized_avg_pool2d_kernel' of similar type ('const int') are easily swapped by mistake [bugprone-easily-swappable-parameters]
16 | const int outW,
| ^~~~~~~~~~~~~~~
17 | const int stride,
| ~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:16:15: note: the first parameter in the range is 'outW'
16 | const int outW,
| ^~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:17:15: note: the last parameter in the range is 'stride'
17 | const int stride,
| ^~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:18:5: warning: 2 adjacent parameters of 'optimized_avg_pool2d_kernel' of similar type ('const int') are easily swapped by mistake [bugprone-easily-swappable-parameters]
18 | const int padding,
| ^~~~~~~~~~~~~~~~~~
19 | const int actual_kernel_size
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:18:15: note: the first parameter in the range is 'padding'
18 | const int padding,
| ^~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:19:15: note: the last parameter in the range is 'actual_kernel_size'
19 | const int actual_kernel_size
| ^~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:22:29: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
22 | const int grid_stride = blockDim.x * gridDim.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:23:42: warning: narrowing conversion from 'int' to 'float' [bugprone-narrowing-conversions]
23 | const float inv_window_size = 1.0f / (actual_kernel_size * actual_kernel_size);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:25:20: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
25 | for (int idx = blockIdx.x * blockDim.x + threadIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:81:19: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
81 | const int N = x.size(0);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:82:19: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
82 | const int C = x.size(1);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:83:19: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
83 | const int H = x.size(2);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:84:19: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
84 | const int W = x.size(3);
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250201_optimize_b10_s4_e0_sweep/level_1/task_45/b8_s3_optimized_avg_pool2d/base/base.cu:96:5: warning: inside a lambda, '__func__' expands to the name of the function call operator; consider capturing the name of the enclosing function explicitly [bugprone-lambda-function-name]
96 | AT_DISPATCH_FLOATING_TYPES(x.scalar_type(), "optimized_avg_pool2d", [&] {
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:237:34: note: expanded from macro 'AT_DISPATCH_FLOATING_TYPES'
237 | AT_DISPATCH_SWITCH(TYPE, NAME, AT_DISPATCH_CASE_FLOATING_TYPES(__VA_ARGS__))
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:233:3: note: expanded from macro 'AT_DISPATCH_CASE_FLOATING_TYPES'
233 | AT_DISPATCH_CASE(at::ScalarType::Double, __VA_ARGS__) \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:74:3: note: expanded from macro 'AT_DISPATCH_CASE'
74 | AT_PRIVATE_CASE_TYPE_USING_HINT(enum_type, scalar_t, __VA_ARGS__)
| ^
note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all)
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/ATen/Dispatch.h:58:7: note: expanded from macro 'AT_PRIVATE_CHECK_SELECTIVE_BUILD'
58 | AT_ERROR( \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:711:32: note: expanded from macro 'AT_ERROR'
711 | C10_EXPAND_MSVC_WORKAROUND(TORCH_CHECK(false, ::c10::str(__VA_ARGS__))); \
| ^
/home/robert_sakana_ai/miniconda3/envs/llm2cuda/lib/python3.11/site-packages/torch/include/c10/util/Exception.h:536:9: note: expanded from macro 'TORCH_CHECK'
536 | __func__, \
| ^