import torch
import torch.nn as nn
import torch.nn.functional as F
def module_fn(
x: torch.Tensor, kernel_size: int, stride: int, padding: int
) -> torch.Tensor:
"""
Applies 2D Average Pooling using functional interface.
Args:
x (torch.Tensor): Input tensor
kernel_size (int): Size of pooling window
stride (int): Stride of pooling operation
padding (int): Input padding
Returns:
torch.Tensor: Output tensor with 2D Average Pooling applied
"""
return F.avg_pool2d(x, kernel_size=kernel_size, stride=stride, padding=padding)
class Model(nn.Module):
"""
Simple model that performs 2D Average Pooling.
"""
def __init__(self, kernel_size: int, stride: int, padding: int):
"""
Initializes the Average Pooling layer.
Args:
kernel_size (int): Size of the pooling window
stride (int): Stride of the pooling operation
padding (int): Padding applied to input tensor
"""
super(Model, self).__init__()
self.kernel_size = kernel_size
self.stride = stride
self.padding = padding
def forward(self, x: torch.Tensor, fn=module_fn) -> torch.Tensor:
"""
Applies 2D Average Pooling to the input tensor.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, channels, height, width)
fn: Function to apply pooling operation, defaults to module_fn
Returns:
torch.Tensor: Output tensor with Average Pooling applied
"""
return fn(
x,
self.kernel_size,
self.stride,
self.padding,
)
batch_size = 16
channels = 64
height = 256
width = 256
kernel_size = 3
stride = None # Defaults to kernel_size
padding = 0
def get_inputs():
x = torch.randn(batch_size, channels, height, width)
return [x]
def get_init_inputs():
return [kernel_size, stride if stride is not None else kernel_size, padding]
import torch
import torch.nn as nn
class Model(nn.Module):
"""
Simple model that performs 2D Average Pooling.
"""
def __init__(self, kernel_size: int, stride: int = None, padding: int = 0):
"""
Initializes the Average Pooling layer.
Args:
kernel_size (int): Size of the pooling window.
stride (int, optional): Stride of the pooling operation. Defaults to None (same as kernel_size).
padding (int, optional): Padding applied to the input tensor. Defaults to 0.
"""
super(Model, self).__init__()
self.avg_pool = nn.AvgPool2d(
kernel_size=kernel_size, stride=stride, padding=padding
)
def forward(self, x: torch.Tensor) -> torch.Tensor:
"""
Applies 2D Average Pooling to the input tensor.
Args:
x (torch.Tensor): Input tensor of shape (batch_size, channels, height, width).
Returns:
torch.Tensor: Output tensor with Average Pooling applied.
"""
return self.avg_pool(x)
batch_size = 16
channels = 64
height = 256
width = 256
kernel_size = 3
stride = None # Defaults to kernel_size
padding = 0
def get_inputs():
x = torch.randn(batch_size, channels, height, width)
return [x]
def get_init_inputs():
return [kernel_size, stride if stride is not None else kernel_size, padding]
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>
// Store frequently accessed read-only offsets for 3x3 pooling in constant memory
// These arrays are small and remain the same for every kernel invocation
__constant__ int pool3_dx[3] = {0, 1, 2};
__constant__ int pool3_dy[3] = {0, 1, 2};
// Kernel that uses constant memory for the fast 3x3 pooling case
template <typename scalar_t>
__global__ void constant_optimized_avg_pool2d_kernel(
const scalar_t* __restrict__ input,
scalar_t* __restrict__ output,
const int N,
const int C,
const int H,
const int W,
const int outH,
const int outW,
const int kernel_size,
const int stride,
const int padding
) {
// Determine spatial position in the output tensor
int tid_x = threadIdx.x;
int tid_y = threadIdx.y;
int out_x = blockIdx.x * blockDim.x + tid_x;
int out_y = blockIdx.y * blockDim.y + tid_y;
// Use blockIdx.z to cover the (N * C) dimension
int nc = blockIdx.z;
if(nc >= N * C) return;
int n = nc / C;
int c = nc % C;
// Check if the computed spatial indices are within output bounds
if (out_x >= outW || out_y >= outH)
return;
// Compute the starting location in the input corresponding to the output element
int in_x_start = out_x * stride - padding;
int in_y_start = out_y * stride - padding;
scalar_t sum = static_cast<scalar_t>(0);
// Fast path: use constant memory for 3x3 pooling when the window is fully inside the input
if (kernel_size == 3 && in_x_start >= 0 && in_y_start >= 0 &&
(in_x_start + 3) <= W && (in_y_start + 3) <= H) {
// Compute the base offset for the (n, c) slice
int base = (n * C + c) * H;
int row = in_y_start;
int col = in_x_start;
sum = input[(base + row + pool3_dy[0]) * W + (col + pool3_dx[0])] +
input[(base + row + pool3_dy[0]) * W + (col + pool3_dx[1])] +
input[(base + row + pool3_dy[0]) * W + (col + pool3_dx[2])] +
input[(base + row + pool3_dy[1]) * W + (col + pool3_dx[0])] +
input[(base + row + pool3_dy[1]) * W + (col + pool3_dx[1])] +
input[(base + row + pool3_dy[1]) * W + (col + pool3_dx[2])] +
input[(base + row + pool3_dy[2]) * W + (col + pool3_dx[0])] +
input[(base + row + pool3_dy[2]) * W + (col + pool3_dx[1])] +
input[(base + row + pool3_dy[2]) * W + (col + pool3_dx[2])];
} else {
// Generic path with boundary checks
for (int ky = 0; ky < kernel_size; ky++) {
int y = in_y_start + ky;
if (y >= 0 && y < H) {
int offset = ((n * C + c) * H + y) * W;
for (int kx = 0; kx < kernel_size; kx++) {
int x = in_x_start + kx;
if (x >= 0 && x < W) {
sum += input[offset + x];
}
}
}
}
}
// Write result to output and normalize by window area
int out_index = ((n * C + c) * outH + out_y) * outW + out_x;
output[out_index] = sum / static_cast<scalar_t>(kernel_size * kernel_size);
}
// Forward function exposed to PyTorch
torch::Tensor constant_optimized_avg_pool2d_forward(
torch::Tensor x,
int kernel_size,
int stride,
int padding
) {
TORCH_CHECK(x.dim() == 4, "Input must be a 4D tensor.");
const int N = x.size(0);
const int C = x.size(1);
const int H = x.size(2);
const int W = x.size(3);
// Calculate output dimensions using standard pooling formula
const int outH = (H + 2 * padding - kernel_size) / stride + 1;
const int outW = (W + 2 * padding - kernel_size) / stride + 1;
auto x_contiguous = x.contiguous();
auto output = torch::empty({N, C, outH, outW}, x.options());
// Configure 2D thread blocks over spatial dimensions with blockIdx.z covering N * C
dim3 threads(32, 8);
dim3 blocks(
(outW + threads.x - 1) / threads.x,
(outH + threads.y - 1) / threads.y,
N * C
);
AT_DISPATCH_FLOATING_TYPES(x.scalar_type(), "constant_optimized_avg_pool2d_kernel", ([&] {
constant_optimized_avg_pool2d_kernel<scalar_t><<<blocks, threads>>>(
x_contiguous.data_ptr<scalar_t>(),
output.data_ptr<scalar_t>(),
N, C, H, W, outH, outW,
kernel_size, stride, padding
);
}));
cudaError_t err = cudaGetLastError();
TORCH_CHECK(err == cudaSuccess, "CUDA Error: ", cudaGetErrorString(err));
return output;
}
PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
m.def("forward", &constant_optimized_avg_pool2d_forward, "Constant Memory Optimized 2D Average Pooling forward (CUDA)");
}
| Metric | Value | Unit | Variance | Samples |
|---|---|---|---|---|
| Executed Ipc Active | 1.644 | inst/cycle | 0.000 | 5 |
| Executed Ipc Elapsed | 1.582 | inst/cycle | 0.000 | 5 |
| Issue Slots Busy | 41.146 | % | 0.142 | 5 |
| Issued Ipc Active | 1.646 | inst/cycle | 0.000 | 5 |
| SM Busy | 41.146 | % | 0.142 | 5 |
| Memory Throughput | 3030767598857.104 | byte/second | 109892805246237622272.000 | 5 |
| Mem Busy | 51.944 | % | 0.030 | 5 |
| Max Bandwidth | 90.436 | % | 0.101 | 5 |
| L1/TEX Hit Rate | 63.770 | % | 0.000 | 5 |
| L2 Hit Rate | 12.826 | % | 0.004 | 5 |
| Mem Pipes Busy | 21.248 | % | 0.017 | 5 |
| Warp Cycles Per Issued Instruction | 31.828 | cycle | 0.053 | 5 |
| Warp Cycles Per Executed Instruction | 31.870 | cycle | 0.054 | 5 |
| Avg. Active Threads Per Warp | 29.330 | 0.000 | 5 | |
| Avg. Not Predicated Off Threads Per Warp | 27.670 | 0.000 | 5 | |
| Max Active Clusters | 0.000 | cluster | 0.000 | 5 |
| Max Cluster Size | 8.000 | block | 0.000 | 5 |
| Overall GPU Occupancy | 0.000 | % | 0.000 | 5 |
| Cluster Occupancy | 0.000 | % | 0.000 | 5 |
| Block Limit SM | 32.000 | block | 0.000 | 5 |
| Block Limit Registers | 8.000 | block | 0.000 | 5 |
| Block Limit Shared Mem | 32.000 | block | 0.000 | 5 |
| Block Limit Warps | 8.000 | block | 0.000 | 5 |
| Theoretical Active Warps per SM | 64.000 | warp | 0.000 | 5 |
| Theoretical Occupancy | 100.000 | % | 0.000 | 5 |
| Achieved Occupancy | 81.808 | % | 0.028 | 5 |
| Achieved Active Warps Per SM | 52.356 | warp | 0.012 | 5 |
| Rule | Description |
|---|---|
| INF HighPipeUtilization | FMA is the highest-utilized pipeline (21.3%) based on active cycles, taking into account the rates of its different instructions. It executes 32-bit floating point (FADD, FMUL, FMAD, ...) and integer (IMUL, IMAD) operations. It is well-utilized, but should not be a bottleneck. |
| INF CPIStall | Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason. |
| WRN Occupancy | This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (81.9%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy. |
| Operation / Metric | Value | Unit |
|---|---|---|
| aten::to | ||
| CPU Time | 579572.85 | μs |
| Device Time | 28620.23 | μs |
| Self CPU Time | 31.91 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::_to_copy | ||
| CPU Time | 579540.95 | μs |
| Device Time | 28620.23 | μs |
| Self CPU Time | 111.83 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| cudaLaunchKernel | ||
| CPU Time | 1058016.01 | μs |
| Device Time | 51804.53 | μs |
| Self CPU Time | 1058016.01 | μs |
| Self Device Time | 51804.53 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void constant_optimized_avg_pool2d_kernel<float>(float const*, float*, int, int, int, int, int, int, int, int, int) | ||
| CPU Time | 0.00 | μs |
| Device Time | 713103.15 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 713103.15 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::zero_ | ||
| CPU Time | 650556.69 | μs |
| Device Time | 532087.09 | μs |
| Self CPU Time | 12343.96 | μs |
| Self Device Time | 0.00 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| aten::fill_ | ||
| CPU Time | 638213.90 | μs |
| Device Time | 532087.09 | μs |
| Self CPU Time | 17017.26 | μs |
| Self Device Time | 532087.09 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
| void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>) | ||
| CPU Time | 0.00 | μs |
| Device Time | 532087.09 | μs |
| Self CPU Time | 0.00 | μs |
| Self Device Time | 532087.09 | μs |
| CPU Memory Usage | 0 | B |
| Device Memory Usage | 0 | B |
| Self CPU Memory Usage | 0 | B |
| Self Device Memory Usage | 0 | B |
45291 warnings generated when compiling for host. Suppressed 45324 warnings (45277 in non-user code, 47 NOLINT). Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.