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55_Matmul_MaxPool_Sum_Scale • fused_divergence_base

Level 2 • Task 55
import torch
import torch.nn as nn
import torch.nn.functional as F


def module_fn(
    x: torch.Tensor,
    kernel_size: int,
    scale_factor: float,
    weight: torch.Tensor,
    bias: torch.Tensor,
) -> torch.Tensor:
    """
    Performs matrix multiplication, max pooling, sum, and scaling.

    Args:
        x (torch.Tensor): Input tensor of shape (batch_size, in_features)
        kernel_size (int): Size of max pooling kernel
        scale_factor (float): Factor to scale the output by
        weight (torch.Tensor): Weight matrix of shape (out_features, in_features)
        bias (torch.Tensor): Bias vector of shape (out_features)

    Returns:
        torch.Tensor: Output tensor of shape (batch_size,)
    """
    x = F.linear(x, weight, bias)
    x = F.max_pool1d(x.unsqueeze(1), kernel_size).squeeze(1)
    x = torch.sum(x, dim=1)
    x = x * scale_factor
    return x


class Model(nn.Module):
    """
    Model that performs matrix multiplication, max pooling, sum, and scaling.
    """

    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(Model, self).__init__()
        gemm = nn.Linear(in_features, out_features)
        self.weight = nn.Parameter(gemm.weight)
        self.bias = nn.Parameter(gemm.bias)

    def forward(self, x, kernel_size, scale_factor, fn=module_fn):
        return fn(x, kernel_size, scale_factor, self.weight, self.bias)


batch_size = 128
in_features = 10
out_features = 5
kernel_size = 2
scale_factor = 0.5


def get_inputs():
    return [torch.randn(batch_size, in_features), kernel_size, scale_factor]


def get_init_inputs():
    return [in_features, out_features, kernel_size, scale_factor]

import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Model that performs matrix multiplication, max pooling, sum, and scaling.
    """
    def __init__(self, in_features, out_features, kernel_size, scale_factor):
        super(Model, self).__init__()
        self.matmul = nn.Linear(in_features, out_features)
        self.max_pool = nn.MaxPool1d(kernel_size)
        self.scale_factor = scale_factor

    def forward(self, x):
        """
        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_features).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_features).
        """
        x = self.matmul(x)
        x = self.max_pool(x.unsqueeze(1)).squeeze(1)
        x = torch.sum(x, dim=1)
        x = x * self.scale_factor
        return x

batch_size = 128
in_features = 10
out_features = 5
kernel_size = 2
scale_factor = 0.5

def get_inputs():
    return [torch.randn(batch_size, in_features)]

def get_init_inputs():
    return [in_features, out_features, kernel_size, scale_factor]
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Kernel Information

Operation Name 55_Matmul_MaxPool_Sum_Scale
Level ID 2
Task ID 55
Kernel Name fused_divergence_base
CUDA Speedup (Native) 3.728x
CUDA Speedup (Compile) 2.232x
CUDA Runtime 0.007 ms
PyTorch Runtime (Native) 0.026 ms
PyTorch Runtime (Compile) 0.016 ms
Correct True
Max Diff (vs. Reference) 0.000000
Model o3-mini-2025-01-31
Temperature 1.00
View Experiment Progress Details

Related Kernels (Level 2, Task 55 • 55_Matmul_MaxPool_Sum_Scale)

Rank Kernel Name Runtime (ms) Speedup Native Speedup Compile
🥇 optimized_shared_warp_base 0.01 3.73 2.23
🥇 smem_accel_base 0.01 3.73 2.23
🥇 indexing_optimized_kernel_base 0.01 3.73 2.23
🥇 warp_divergence_min_optimized_base 0.01 3.73 2.23
🥇 divergence_free_warp_base_base 0.01 3.73 2.23
🥇 optimized_divergence_free_kernel_base 0.01 3.73 2.23
🥇 min_warp_div_kernel_base 0.01 3.73 2.23
🥇 optimized_reduction_shfl_base 0.01 3.73 2.23
🥇 blocksize_tuning_opt_base 0.01 3.73 2.23
🥇 optimized_warp_shared_kernel_base 0.01 3.73 2.23
🥇 fused_divergence_base 0.01 3.73 2.23
🥇 optimized_hybrid_matmul_pool_base 0.01 3.73 2.23
🥇 optimized_hybrid_kernel_base 0.01 3.73 2.23
🥇 evenly_distributed_kernel_base 0.01 3.73 2.23
🥇 warp_reduction_opt_kernel_base_base 0.01 3.73 2.23
🥇 unrolled_matmul_pool_base_base 0.01 3.73 2.23
🥇 hybrid_min_sync_kernel_base 0.01 3.73 2.23
🥇 uniform_no_div_kernel_base 0.01 3.73 2.23
🥇 shared_warp_optimized_base 0.01 3.73 2.23
🥇 optimized_divergence_free_kernel_base 0.01 3.73 2.23 
#include <torch/extension.h>
#include <cuda.h>
#include <cuda_runtime.h>

// This kernel fuses the linear transformation (matrix multiplication + bias addition) with a max pooling and summation stage.
// Each block processes one sample from the batch. The computed output vector is stored in shared memory to avoid writing
// an intermediate result to global memory. We use warp-level primitives (__shfl_down_sync) to efficiently reduce 
// the partial sums from the max pooling operation.

__global__ void fused_divergence_kernel(
    const float* __restrict__ x,
    const float* __restrict__ weight,
    const float* __restrict__ bias,
    float* __restrict__ output,
    int B,          // batch size
    int inF,        // number of input features
    int outF,       // number of output features
    int kernel_size,
    float scale_factor
) {
    const int warp_size = 32;
    const int lane_id = threadIdx.x % warp_size;
    const int warp_id = threadIdx.x / warp_size;
    const int block_threads = blockDim.x;
    const int warps_per_block = block_threads / warp_size;

    // Each block processes one sample in the batch
    int b = blockIdx.x;
    if (b >= B) return;

    // Use shared memory to store the linear transformation results and warp partial sums.
    // Assumed shared memory size: (outF + warps_per_block) floats
    extern __shared__ float sdata[];
    float* linear_out = sdata;             // holds linear transformation results (size: outF)
    float* warp_sum   = &sdata[outF];        // holds partial pooling sums from each warp

    // Partition the output features among warps
    int features_per_warp = (outF + warps_per_block - 1) / warps_per_block;
    int start_feature = warp_id * features_per_warp;
    int end_feature = min(start_feature + features_per_warp, outF);

    // Compute the linear transformation: out[j] = bias[j] + dot(x[b], weight[j])
    // Each warp processes its assigned chunk with vectorized thread-level parallelism
    for (int j = start_feature + lane_id; j < end_feature; j += warp_size) {
        float sum = bias[j];
        const float* w_row = weight + j * inF;  // row for output feature j
        const float* x_row = x + b * inF;
        #pragma unroll 4
        for (int i = 0; i < inF; i++) {
            sum += x_row[i] * w_row[i];
        }
        linear_out[j] = sum;
    }
    __syncthreads();

    // Compute pooling segments
    // The pooling is performed over segments of size 'kernel_size' along the output feature dimension.
    int pooled_len = (outF >= kernel_size) ? (1 + (outF - kernel_size) / kernel_size) : 0;

    // Each thread processes multiple segments in a round-robin fashion
    float thread_partial_sum = 0.0f;
    for (int seg = threadIdx.x; seg < pooled_len; seg += block_threads) {
        int seg_start = seg * kernel_size;
        float seg_max = linear_out[seg_start];
        // Compute the max in this pooling segment
        for (int k = 1; k < kernel_size; k++) {
            int idx = seg_start + k;
            if (idx < outF) {
                float val = linear_out[idx];
                seg_max = (val > seg_max) ? val : seg_max;
            }
        }
        thread_partial_sum += seg_max;
    }

    // Warp-level reduction of the partial sums (using shuffle operations)
    for (int offset = warp_size/2; offset > 0; offset /= 2) {
        thread_partial_sum += __shfl_down_sync(0xffffffff, thread_partial_sum, offset);
    }

    // First lane of each warp writes its result to shared memory
    if (lane_id == 0) {
        warp_sum[warp_id] = thread_partial_sum;
    }
    __syncthreads();

    // Final reduction among warp results by the first warp
    if (warp_id == 0) {
        float block_sum = (lane_id < warps_per_block) ? warp_sum[lane_id] : 0.0f;
        for (int offset = warp_size/2; offset > 0; offset /= 2) {
            block_sum += __shfl_down_sync(0xffffffff, block_sum, offset);
        }
        if (lane_id == 0) {
            output[b] = block_sum * scale_factor;
        }
    }
}


at::Tensor forward(
    at::Tensor x,
    int64_t kernel_size,
    double scale_factor,
    at::Tensor weight,
    at::Tensor bias
) {
    TORCH_CHECK(x.is_cuda(), "x must be a CUDA tensor");
    TORCH_CHECK(weight.is_cuda(), "weight must be a CUDA tensor");
    TORCH_CHECK(bias.is_cuda(), "bias must be a CUDA tensor");
    TORCH_CHECK(x.dim() == 2, "x must have shape (batch_size, in_features)");
    TORCH_CHECK(weight.dim() == 2, "weight must have shape (out_features, in_features)");
    TORCH_CHECK(bias.dim() == 1, "bias must have shape (out_features)");

    const auto B = x.size(0);
    const auto inF = x.size(1);
    const auto outF = weight.size(0);

    auto out = torch::empty({B}, x.options());

    // Configure kernel launch parameters
    const int threads_per_block = 256;
    const int warps_per_block = threads_per_block / 32;
    // Shared memory: space for 'outF' floats (for linear results) + one float per warp for reduction
    size_t shared_mem_bytes = (outF + warps_per_block) * sizeof(float);

    // Launch one block per sample in the batch
    fused_divergence_kernel<<<B, threads_per_block, shared_mem_bytes>>>(
        x.data_ptr<float>(),
        weight.data_ptr<float>(),
        bias.data_ptr<float>(),
        out.data_ptr<float>(),
        B,
        inF,
        outF,
        static_cast<int>(kernel_size),
        static_cast<float>(scale_factor)
    );

    return out;
}

PYBIND11_MODULE(TORCH_EXTENSION_NAME, m) {
    m.def("forward", &forward, "Fused CUDA kernel for linear transformation and pooling");
}
Performance Metrics
Metric Value Unit Variance Samples
Executed Ipc Active 0.406 inst/cycle 0.000 5
Executed Ipc Elapsed 0.190 inst/cycle 0.000 5
Issue Slots Busy 10.328 % 0.014 5
Issued Ipc Active 0.412 inst/cycle 0.000 5
SM Busy 10.328 % 0.014 5
Memory Throughput 3826795137.838 byte/second 1578904254527787.500 5
Mem Busy 7.024 % 0.003 5
Max Bandwidth 3.738 % 0.001 5
L1/TEX Hit Rate 89.620 % 0.000 5
L2 Hit Rate 105.856 % 0.007 5
Mem Pipes Busy 3.402 % 0.001 5
Warp Cycles Per Issued Instruction 18.350 cycle 0.638 5
Warp Cycles Per Executed Instruction 18.648 cycle 0.661 5
Avg. Active Threads Per Warp 19.560 0.000 5
Avg. Not Predicated Off Threads Per Warp 15.990 0.000 5
Max Active Clusters 0.000 cluster 0.000 5
Max Cluster Size 8.000 block 0.000 5
Overall GPU Occupancy 0.000 % 0.000 5
Cluster Occupancy 0.000 % 0.000 5
Block Limit SM 32.000 block 0.000 5
Block Limit Registers 8.000 block 0.000 5
Block Limit Shared Mem 28.000 block 0.000 5
Block Limit Warps 8.000 block 0.000 5
Theoretical Active Warps per SM 64.000 warp 0.000 5
Theoretical Occupancy 100.000 % 0.000 5
Achieved Occupancy 11.530 % 0.000 5
Achieved Active Warps Per SM 7.376 warp 0.000 5
Analysis Rules
Rule Description
WRN HighPipeUtilization All compute pipelines are under-utilized. Either this kernel is very small or it doesn't issue enough warps per scheduler. Check the Launch Statistics and Scheduler Statistics sections for further details.
WRN ThreadDivergence Instructions are executed in warps, which are groups of 32 threads. Optimal instruction throughput is achieved if all 32 threads of a warp execute the same instruction. The chosen launch configuration, early thread completion, and divergent flow control can significantly lower the number of active threads in a warp per cycle. This kernel achieves an average of 19.6 threads being active per cycle. This is further reduced to 16.0 threads per warp due to predication. The compiler may use predication to avoid an actual branch. Instead, all instructions are scheduled, but a per-thread condition code or predicate controls which threads execute the instructions. Try to avoid different execution paths within a warp when possible. In addition, ensure your kernel makes use of Independent Thread Scheduling, which allows a warp to reconverge after a data-dependent conditional block by explicitly calling __syncwarp().
WRN Occupancy This kernel's theoretical occupancy is not impacted by any block limit. The difference between calculated theoretical (100.0%) and measured achieved occupancy (11.5%) can be the result of warp scheduling overheads or workload imbalances during the kernel execution. Load imbalances can occur between warps within a block as well as across blocks of the same kernel. See the CUDA Best Practices Guide (https://docs.nvidia.com/cuda/cuda-c-best-practices-guide/index.html#occupancy) for more details on optimizing occupancy.
INF CPIStall Check the Warp Stall Sampling (All Cycles) table for the top stall locations in your source based on sampling data. The Kernel Profiling Guide (https://docs.nvidia.com/nsight-compute/ProfilingGuide/index.html#metrics-reference) provides more details on each stall reason.
Operation / Metric Value Unit
aten::to
CPU Time 360687.58 μs
Device Time 5.54 μs
Self CPU Time 54.13 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::_to_copy
CPU Time 360633.45 μs
Device Time 5.54 μs
Self CPU Time 108.18 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::empty_strided
CPU Time 360399.73 μs
Device Time 0.00 μs
Self CPU Time 105.88 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaDeviceGetStreamPriorityRange
CPU Time 349247.48 μs
Device Time 0.00 μs
Self CPU Time 349247.48 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaLaunchKernel
CPU Time 496434.69 μs
Device Time 21431.83 μs
Self CPU Time 496434.69 μs
Self Device Time 21431.83 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
fused_divergence_kernel(float const*, float const*, float const*, float*, int, int, int, int, float)
CPU Time 0.00 μs
Device Time 33619.60 μs
Self CPU Time 0.00 μs
Self Device Time 33619.60 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
cudaEventRecord
CPU Time 18188.18 μs
Device Time 42623.30 μs
Self CPU Time 18188.18 μs
Self Device Time 42623.30 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::zero_
CPU Time 65316.50 μs
Device Time 636462.38 μs
Self CPU Time 13060.54 μs
Self Device Time 0.00 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
aten::fill_
CPU Time 52257.87 μs
Device Time 636462.38 μs
Self CPU Time 17300.80 μs
Self Device Time 636462.38 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
void at::native::vectorized_elementwise_kernel<4, at::native::FillFunctor<int>, at::detail::Array<char*, 1> >(int, at::native::FillFunctor<int>, at::detail::Array<char*, 1>)
CPU Time 0.00 μs
Device Time 636462.38 μs
Self CPU Time 0.00 μs
Self Device Time 636462.38 μs
CPU Memory Usage 0 B
Device Memory Usage 0 B
Self CPU Memory Usage 0 B
Self Device Memory Usage 0 B
Status: Completed 
45294 warnings generated when compiling for host.
Suppressed 45325 warnings (45278 in non-user code, 47 NOLINT).
Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:11:5 bugprone-easily-swappable-parameters
11 | const float* __restrict__ x,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
12 | const float* __restrict__ weight,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 | const float* __restrict__ bias,
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:11:31: note: the first parameter in the range is 'x'
11 | const float* __restrict__ x,
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:13:31: note: the last parameter in the range is 'bias'
13 | const float* __restrict__ bias,
| ^~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:15:5: warning: 3 adjacent parameters of 'fused_divergence_kernel' of similar type ('int') are easily swapped by mistake [bugprone-easily-swappable-parameters]
15 | int B, // batch size
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 | int inF, // number of input features
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
17 | int outF, // number of output features
| ~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:15:9: note: the first parameter in the range is 'B'
15 | int B, // batch size
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:17:9: note: the last parameter in the range is 'outF'
17 | int outF, // number of output features
| ^~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:18:5: warning: 2 adjacent parameters of 'fused_divergence_kernel' of convertible types are easily swapped by mistake [bugprone-easily-swappable-parameters]
18 | int kernel_size,
| ^~~~~~~~~~~~~~~~
19 | float scale_factor
| ~~~~~~~~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:18:9: note: the first parameter in the range is 'kernel_size'
18 | int kernel_size,
| ^~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:19:11: note: the last parameter in the range is 'scale_factor'
19 | float scale_factor
| ^~~~~~~~~~~~
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:19:5: note: 'int' and 'float' may be implicitly converted
19 | float scale_factor
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:22:25: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
22 | const int lane_id = threadIdx.x % warp_size;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:23:25: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
23 | const int warp_id = threadIdx.x / warp_size;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:24:31: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
24 | const int block_threads = blockDim.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:28:13: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
28 | int b = blockIdx.x;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:46:30: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' [bugprone-implicit-widening-of-multiplication-result]
46 | const float* w_row = weight + j * inF; // row for output feature j
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:46:39: note: make conversion explicit to silence this warning
4 | const float* w_row = weight + j * inF; // row for output feature j
| ^~~~~~~
| static_cast<ptrdiff_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:46:39: note: perform multiplication in a wider type
46 | const float* w_row = weight + j * inF; // row for output feature j
| ^
| static_cast<ptrdiff_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:47:30: warning: result of multiplication in type 'int' is used as a pointer offset after an implicit widening conversion to type 'ptrdiff_t' [bugprone-implicit-widening-of-multiplication-result]
47 | const float* x_row = x + b * inF;
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:47:34: note: make conversion explicit to silence this warning
47 | const float* x_row = x + b * inF;
| ^~~~~~~
| static_cast<ptrdiff_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:47:34: note: perform multiplication in a wider type
47 | const float* x_row = x + b * inF;
| ^
| static_cast<ptrdiff_t>( )
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:62:20: warning: narrowing conversion from 'unsigned int' to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
62 | for (int seg = threadIdx.x; seg < pooled_len; seg += block_threads) {
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:101:16: warning: the parameter 'x' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
101 | at::Tensor x,
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:104:16: warning: the parameter 'weight' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
104 | at::Tensor weight,
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:105:16: warning: the parameter 'bias' is copied for each invocation but only used as a const reference; consider making it a const reference [performance-unnecessary-value-param]
105 | at::Tensor bias
| ^
| const &
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:132:9: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
132 | B,
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:133:9: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
133 | inF,
| ^
/home/robert_sakana_ai/llm_cuda/experiments/20250203_optimize_b10_s4_e0_sweep/level_2/task_55/b4_s1_fused_divergence/base/base.cu:134:9: warning: narrowing conversion from 'int64_t' (aka 'long') to signed type 'int' is implementation-defined [bugprone-narrowing-conversions]
134 | outF,
| ^